• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.391-393
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• 2004

For performance and stability of a synchronized system, we need an efficient Clock Tree Synthesis(CTS) methodology to design clock distribution networks. In a system-on-a-chip(SOC) design environment, CTS effectively distributes clock signals from clock sources to synchronized points on layout design. In this paper, we suggest the pre-layout analysis of the clock network including gated clock, multiple clock, and test mode CTS optimization. This analysis can help to avoid design failure with potential CTS problems from logic designers and supply layout constraints so as to get an optimal clock distribution network. Our new design flow including pre-layout CTS analysis and structural violation checking also contributes to reduce design time significantly.

• ETRI Journal
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• v.36 no.6
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• pp.931-941
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• 2014

Many methodologies for clock mesh networks have been introduced for two-dimensional integrated circuit clock distribution networks, such as methods to reduce the total wirelength for power consumption and to reduce the clock skew variation through consideration of buffer placement and sizing. In this paper, we present a methodology for clock mesh to reduce both the clock skew and the total wirelength in three-dimensional integrated circuits. To reduce the total wirelength, we construct a smaller mesh size on a die where the clock source is not directly connected. We also insert through-silicon vias (TSVs) to distribute the clock signal using an effective clock TSV insertion algorithm, which can reduce the total wirelength on each die. The results of our proposed methods show that the total wirelength was reduced by 12.2%, the clock skew by 16.11%, and the clock skew variation by 11.74%, on average. These advantages are possible through increasing the buffer area by 2.49% on the benchmark circuits.

• Journal of information and communication convergence engineering
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• v.8 no.3
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• pp.339-342
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• 2010

An iris image pattern positioning with preserved edge detector, ring zone and clock zone, frequency distribution and overlay matching is presented in this paper. Edge detector is required to be powerful and detail. That is proposed by overlaying Canny with LOG (CLOG). The two reference patterns are made from allocating each gray level on the clock zone and ring zone respectively. The normalized target image is overlaid with the clock zone reference pattern and the ring zone pattern to extract overlapped number, and make a matched frequency distribution to look through a symptom and position of human organ and tissue. The iterating experiments result in the ring and clock zone positioning evaluation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.1-8
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• 2004

A novol clock distribution scheme is proposed for high-speed and low-power digital system to minimize clock skew and reduce dynamic power consumption. This scheme has ideal zero-skew characteristic by using folded clock lines (FCL) and phase blending circuit. For analyzing suitable line structures to FCLs, microstrip line and coplanar line are placed with folded clock lines. Simulation results show that the maximum clock-skew between two receivers located 10mm apart is less than lops at 1㎓ and the maximum clock-skew between two receivers located 20mm apart is less than 60ps at 1㎓. Also the results show that the minimum skews of clock signals regardless of process, voltage, and temperature variation are invariant.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.9
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• pp.1633-1640
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• 2006

The problem of reducing power dissipation while simultaneously delivering acceptable levels of performance is becoming a critical concern in high pelf[mann system design. In this paper, we present this power dissipation problem from the clock generation and distribution side. We examine clock power efficiency and several applications as well as wireless communication circuits.

• Progress in Superconductivity and Cryogenics
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• v.8 no.2
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• pp.17-19
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• 2006

A novel clock distribution technique for pipelined-RSFQ logics using variable Bias Currents of JTLs as delay-medium is newly proposed. RSFQ logics consist of several logic gates or blocks connected in a pipeline structure. And each block has variable delay difference. In the structure, this clock distribution method generates a set of clock signals for each logic blocks with suitable corresponding delays. These delays, in the order of few to tens of pS, can be adjusted through controlling bias current of JTL of delay medium. While delays with resistor value and JJ size are fixed at fabrication stage, delay through bias current can be controlled externally, and thus, is heavily investigated for its range as well as correct operation within current margin. Possible ways of a standard delay library with modular structure are sought for further modularizing Pipelined-RSFQ applications. Simulations and verifications are done through WRSpice with Hypres 3-um process parameters.

• Journal of information and communication convergence engineering
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• v.6 no.4
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• pp.383-390
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• 2008

Clock skew modeling is important in the performance evaluation and prediction of clock distribution network and it is one of the major constraints for high-speed operation of synchronous integrated circuits. In clock routing synthesis, it is necessary to reduce the clock skew under the specified skew bound, while minimizing the cost such as total wire length and delay. In this paper, a new efficient bounded clock skew routing method is described, which generalizes the well-known bounded skew tree method by allowing loops, i.e., link-edges can be inserted to a clock tree when they are beneficial to reduce the clock skew and/or the wire length. Furthermore, routing topology construction and wire sizing is used to reduce clock delay.

• Animal cells and systems
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• v.16 no.1
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• pp.1-10
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• 2012

Most living organisms synchronize their physiological and behavioral activities with the daily changes in the environment using intrinsic time-keeping systems called circadian clocks. In mammals, the key molecular features of the internal clock are transcription- and translational-based negative feedback loops, in which clock-specific transcription factors activate the periodic expression of their own repressors, thereby generating the circadian rhythms. CLOCK and BMAL1, the basic helix-loop-helix (bHLH)/PAS transcription factors, constitute the positive limb of the molecular clock oscillator. Recent investigations have shown that various levels of posttranslational regulation work in concert with CLOCK/BMAL1 in mediating circadian and cellular stimuli to control and reset the circadian rhythmicity. Here we review how the CLOCK and BMAL1 activities are regulated by intracellular distribution, posttranslational modification, and the recruitment of various epigenetic regulators in response to circadian and cellular signaling pathways.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.37-42
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• 2007

Clock grid networks are now common in most high performance microprocessors. This paper presents a new effective modeling and simulation methodology for the clock grid using scattering parameter. It also shows the effect of wire width and grid size on the clock skew of the grid. The interconnection of the clock grid is modeled by RC passive elements. The results show that the error is within 10 % comparing to Hspice simulation results.

• Journal of Communications and Networks
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• v.8 no.1
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• pp.8-12
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• 2006

Master-slave (M-S) strategies implemented with chain circuits are the main option in order to distribute clock signals along synchronous networks in several telecommunication and control applications. Here, we study the two types of masterslave chains: Without clock feedback, i.e., one-way master-slave (OWMS) and with clock feedback, i.e., two-way master-slave (TWMS) considering the slave nodes as second-order phase-locked loops (PLL) for several types of loop low-pass filters.