• IEMEK Journal of Embedded Systems and Applications
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• v.16 no.4
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• pp.119-127
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• 2021

The aim of this paper is to propose a less conservative stabilization condition for leader-following sampled-data control of wheeled mobile robot (WMR) systems by using a clock-dependent Lyapunov function (CDLF) with looped functionals. In the leader-following WMR system, the state and input of the leader robot are measured by digital devices mounted on the following robot, and they are utilized to construct the sampled-data controller of the following robot. To design the sampled-data controller, a stabilization condition is derived by using the CDLF with looped functionals, and formulated in terms of sum of squares (SOS). The considered Lyapunov function is a polynomial form with respect to the clock related to the transmitted sampling instants. As the degree of the Lyapunov function increases, the stabilization condition becomes less conservative. This ensures that the designed controller is able to stabilize the system with a larger maximum sampling interval. The simulation results are provided to demonstrate the effectiveness of the proposed method.

• Journal of Photoscience
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• v.9 no.2
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• pp.240-242
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• 2002

In Drosophila melanogaster, it is known that the circadian clock consists of an autoregulatory feedback loop, which includes so-called clock genes, such as per, tim, dClk and cyc and produces periodical expression of per. It is recently suggested, however, that the circadian oscillation without the rhythmical expression of per is involved in the regulation of circadian locomotor rhythms. In the present study, we examined the existence and the property of the possible per-less oscillation using arrhythmic clock mutant flies carrying per$^{01}$, tim$^{01}$, dClk$^{Jrk}$ or cyc$^{01}$. When temperature cycles consisting of 25$^{\circ}$Ｃ and 30$^{\circ}$Ｃ with varying periods (T = 8~32 hr) were given, they showed rhythms synchronizing with the given cycle under constant darkness (DD). per$^{01}$ and tim$^{01}$ flies always showed a peak around 7 hr after the onset of thermophase irrespective of Ts of temperature cycles, while dClk$^{Jrk}$ and cyc$^{01}$ flies did not. In addition, several days were necessary to establish a clear temperature entrainment in per$^{01}$ and tim$^{01}$ flies, when they were transferred from a constant temperature to a temperature cycle under DD. These results suggest that per$^{01}$ and tim$^{01}$ flies have a temperature-entrainable weak oscillatory mechanism. The fact that dClk$^{Jrk}$ and cyc$^{01}$ flies did not show any sign of the endogenous oscillation suggests that the per-less oscillatory mechanism may require CLK and CYC.

• Journal of Photoscience
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• v.9 no.2
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• pp.246-248
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• 2002

Light is a major environmental signal for entrainment of the circadian clock, but little is known about the phototransduction pathway triggered by light-activation of photoreceptive molecule(s) responsible for the phase shift of the clock in vertebrates. The chicken pineal gland and retina contain the autonomous circadian oscillators together with the photic entrainment pathway, and hence they provide useful experimental model for the clock system. We previously demonstrated the expression and light-dependent activation of rod-type transducin $\alpha$-subunit (Gtl$\alpha$) in the chicken pineal gland. It is unlikely, however, that the pineal Gt$_1$$\alpha$ plays a major role in the photic entrainment, because the light-induced phase shift is unaffected by bloking the signaling function of Gt$_1$$\alpha$. Here, we show the expression of G 11 $\alpha$, an $\alpha$-subunit of another heterotrimeric G-protein, in the chicken pineal gland and retina by cDNA cloning, Northern blot and Western blot analyses. GIl$\alpha$-immunoreactivity was colocalized with pinopsin in the chicken pineal cells and it was found predominantly at the outer segments of photoreceptor cells in the retinal sections, suggesting functional coupling of G11 $\alpha$ with opsins in the both the tissues. By coimmunoprecipitation experiments using the retina, we showed the light- and GTP-dependent interaction between rhodopsin and G11 $\alpha$. Upon ectopic expression of a Gq/ 11-coupled receptor in cultured pineal cells, pharmacological (non-photic) activation of endogenous G11 induced phase-dependent phase shifts of the melatonin rhythm in a manner very similar to the effect of light. These results suggested opsin-G11 pathway contributing to the photic entrainment of the circadian clock.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.68-70
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• 1998

본 논문에서는 클록들을 주기적으로 동기화하는 분산 실시간 시스템에서 주어진 태스크의 시간 제약(timing constraint)을 변환시는 구가지 기법을 제안한다. 전형적인 이산 클록 동기화(discrete clock synchronization)알고리즘은 클록의 값을 순간적으로 보정(correct)하여 클록의 시간이 불연속적으로 진행학 한다. 이러한 시간상의 불연속성은 태스크의 시작제한시간(release time)이나 종료시한(deadline)과 같은 이벤트를 잃어버리거나 다시 발생시키는 오류를 범하게 한다. 클록 시간의 불연속성을 피하기 위해 일반적으로 연속 클록 동기화(continuous clock synchronization) 기법이제안되었지만 소프트웨어적으로 구현되기에는 많은 오버헤드를 유발시키는 문제점이 있다. 이에 따라 연속 클록 동기화는 PLL (Phase-Locked Loop)을 이용한 별도의 하드웨어를 사용하는 것이 보통이다. 본 논문에서는 연속 클록 동기화 기법을 사용하는 대신, 태스크의 시간 제약을 동적으로 변환시키는 DCT (Dynamic Constraint Transformation) 기법을 제안하였다. DCT는 소프트웨어 으로 구현이 가능하여 새로운 하드웨어를 필요로 하지 않으며, 이를 통해 기존의 이산적으로 동기화된 시스템에서 클록 시간의 불연속성에 의한 문제점들을 해결할 수 있다. 또 다른 문제점으로서, 클록의 물리적인 특성으로 인해 동기화된 클록들이 상한된(bounded from the above)오차(skew)를 갖는다는 것이다. 이러한 오차는 지역 클록(local clock)에 대해 만족될 수 있는 임의의 실기간 제약 조건이 전역 클록(global clock)에 대해서는 만족되지 않을 수 있음을 의미한다. 본 논문에서는 이를 위해 먼저 두 가지의 스케줄링 가능성, 지역적 스케줄링 가능서(local schedulability)과 전역적 스케줄링 가능성(global schedulability)을 정의하고, 실시간 제약을 정적으로 변환시키는 SCT (Static Constraint Transformation)기법을 제안하였다. SCT를 통해 지역적으로 스케줄링 가능한 태스크는 전역적으로 스케줄링이 가능하므로, 단지 지역적 스케줄링 가능성만을 검사하면서 스케줄링 문제를 해결할 수 있도록 하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.95-98
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• 2012

This paper describes a multiphase delay-locked loop (DLL) that generates a 32-phase output clock over the operating frequency range of 40 MHz to 280 MHz. The matrix-based delay line is used for high resolution of 1-bit delay. A calibration scheme, which improves the linearity of a delay line, is achieved by calibrating the nonlinearity of the input stage of the matrix. The multi-phase DLL is fabricated by using 0.11-${\mu}m$ CMOS process with a 1.2 V supply. At the operating frequency of 125MHz, the measurement results shows that the DNL is less than +0.51/-0.12 LSB, and the measured peak-to-peak jitter of the multi-phase DLL is 30 ps with input peak-to-peak jitter of 12.9 ps. The area and power consumption of the implemented DLL are $480{\times}550{\mu}m^2$ and 9.6 mW at the supply voltage of 1.2 V, respectively.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.6
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• pp.669-675
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• 2014

In this paper, we described the investigated theoretical time synchronization performances and experiment results obtained by commercially provided PTP (Precise Time Protocol) modules when the time of a slave clock is synchronized to the master clock. In the case of the theoretical performance analysis, we investigated 3 types of clock levels such as Crystal Oscillator (XO), TCXO (Temperature Compensated XO) and OCXO (Oven Controlled XO). From the analysis, it was observed that the synchronization performance is greatly influenced by the synchronization period and the required performance under 1 us can be achieved by using XO level clocks when the synchronization period is less than 2 seconds and the uncertainty of the propagation delay is under 100 ns. For the experiments using commercial PTP modules, the synchronization performance was investigated for direct, through 1 hub and through 2 hubs connections between the master clock and the slave clock. From the experiment results, we observed that time synchronization under 90 ns with 1,000 seconds observation interval can be achieved in the case of direct connection.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.10
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• pp.7-13
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• 2010

A compact phase interpolator (PI) based spread spectrum clock generator (SSCG) for electromagnetic interference (EMI) reduction is presented. The proposed SSCG utilizes a digitally controlled phase interpolation technique to achieve triangular frequency modulation with less design complexity and small power and area overhead. The novel SSCG can generate the system clock with a programmable center-spread spectrum range of up to +/- 2 % at 200 MHz, while maintaining the clock duty cycle ratio without distortions. The PI-based SSCG has been designed and evaluated in 0.18-um 1.8-V CMOS technology, which consumes about 5.0 mW at 200MHz and occupies a chip size of $0.092mm^2$ including a DLL.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.44-49
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• 2008

We have proposed a clock recovery circuit for 13.56MHz RFID Tags using 100%, ASK RF input signal. The proposed clock recovery circuit generates clock pulses without reference clock by adapting register controlled DLL. The proposed circuit have designed by using a TSMC 0.18um 1P6M CMOS technology. The simulated results show that the phase locking time of the proposed circuit is about 6.4 usec and power consumption is about 43uW at supply voltage of 3.3V.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.156-164
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• 2014

In a delay line type of a time-to-digital converter implemented in Field Programmable Gate Array, the timing accuracy decreases for a longer carry chain. In this paper, we propose a structure that has a multi-phase clock and a state machine to check metastability; this would reduce the required length of the carry chain with the same time resolution. To reduce the errors caused by the time difference in the four delay lines associated with a four-phase clock, the proposed TDC generates a single input pulse from four phase clocks and uses a single delay line. Moreover, the state machine is designed to find the phase clock that is used to generate the single input pulse and determine the metastable state without a synchronizer. With the measurement range of 1 ms, the measured resolution was 22 ps, and the non-linearity was 25 ps.

• Journal of the Korea Society of Computer and Information
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• v.25 no.1
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• pp.71-77
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• 2020

In this paper, we propose a method in which PingPong256 combines LFSR and variable clock to generate an irregular PRNG and use it for image encryption. PingPong256 is guaranteed an extended period based on the two LFSRs, and the variable clock is a structure that outputs the result of operating a predetermined clock in one operation by referring to the state of the different LFSR. A variable clock is characterized by the difficulty of predicting the output at any time because the choice increases with time. PingPong256 combines the advantages of LFSR and variable clock, the convenience of hardware and software implementation, and the benefits of sensitivity and irregular periods. Also, the statistical safety was verified using the NIST SP800-22, the safety of the proposed method, and the sensitivity of the image change was tested using NPCR and UACI.