• Journal of KIISE:Computing Practices and Letters
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• v.11 no.3
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• pp.216-223
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• 2005

A computer clock has limits in accuracy and precision affected by its inherent instability, the environment elements, the modification of users, and errors of the system. So the computer clock needs to be synchronized with a standard clock if the computer system requires the precise time processing. The purpose of synchronizing clocks is to provide a global time base throughout a distributed system. Once this time base exists, transactions among members of distributed system can be controlled based on time. This paper discusses the integrated approach to clock synchronization. An embedded system is considered for time synchronization based on the GPS(Global Positioning System) referenced time distribution model. The system uses GPS as standard reference time source and offers UTC(Universal Time Coordinated) through NTP(Network Time Protocol). A clock model is designed and adapted to keep stable time and to provide accurate standard time with precise resolution. Private MIB(Management Information Base) is defined for network management. Implementation results and performance analysis are also presented.

• Korean Journal of Optics and Photonics
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• v.16 no.1
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• pp.21-26
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• 2005

10 GHz clock recovery from 40 Gbit/s optical time-division-multiplexed(OTDM) signal pulses was experimentally demonstrated using an optical phase lock loop based on a terahertz optical asymmetric demultiplexer(TOAD) with a local-reference-oscillator-free electronic feedback circuit. The 10 GHz clock was successfully extracted from 40 Gbit/s signals. The SNR of the time-extracted 10 GHz RF signal to the side components was larger than 40 dB. Also we performed numerical simulation about the extraction process of phase information in TOAD. The lock-in frequency range of the clock recovery is found to be 10 kHz.

• Journal of Korea Society of Industrial Information Systems
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• v.20 no.4
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• pp.39-45
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• 2015

In this paper, variable rate CDR(Clock and Data Recovery) circuit adopting blind oversampling architecture is presented. The clock recovery circuit is implemented by using wide range voltage controlled oscillator and band selection method and the data recovery circuit is designed to digital circuit used majority voting method in order to low power and small area. The designed low power variable clock and data recovery is implemented by wide range voltage controlled oscillator and digital data recovery circuit. The designed variable rate CDR is operated from 10 bps to 2 Mbps. The total power consumption is about 4.4mW at 1MHz clock. The supply voltage is 1.2V. The designed die area is $120{\mu}m{\times}75{\mu}m$ and this circuit is fabricated in $0.13{\mu}m$ CMOS process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.2
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• pp.408-414
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• 2014

This paper proposes a charge-pump phase-locked loop (PLL) with 51-phase output clock of a 125 MHz target frequency. The proposed PLL uses three voltage controlled oscillators (VCOs) to generate 51-phase clock and increase of maximum operating frequency. The 17 delay-cells consists of each VCO, and a resistor averaging scheme which reduces the phase mismatch among 51-phase clock combines three VCOs. The proposed PLL uses a 65 nm 1-poly 9-metal CMOS process with 1.0 V supply. The simulated peak-to-peak 지터 of output clock is 0.82 ps at an operating frequency of 125 MHz. The differential non-linearity (DNL) and integral non-linearity (INL) of the 51-phase output clock are -0.013/+0.012 LSB and -0.033/+0.041 LSB, respectively. The operating frequency range is 15 to 210 MHz. The area and power consumption of the implemented PLL are $580{\times}160{\mu}m^2$ and 3.48 mW, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.8
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• pp.889-895
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• 2019

It is not easy to keep time promises in the complex daily lives. Especially, the increase in the number of vehicles causes traffic congestion in commuting time, which results in the delayed arrival and varies greatly depending on the weather conditions. In this paper, proposed is a smart alarm clock that automatically adjusts the alarm time according to weather conditions and suggests ways to deal with traffic congestion. The proposed smart alarm clock is designed to operate the functions of a normal alarm clock using touch functionality. In addition, it is designed to find weather information using open API and to automatically change alarm time to prepare for expected time delay. The proposed design was implemented based on Arduino Mega2560 and a touch TFT-LCD. WiFi module for internet connection, RTC module for clock function and MP3 player module for alarm sound playback were used together. The proposed design has been filed as a patent and is currently under review.

• Journal of IKEEE
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• v.26 no.4
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• pp.714-721
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• 2022

A phase-locked loop (PLL)-based frequency synthesizer is proposed for a system on a chip (SoC) using multi-frequency clock signals. The proposed PLL-based frequency synthesizer consists of a charge pump PLL which is implemented by a phase frequency detector (PFD), a charge pump (CP), a loop filter, a voltage controlled oscillator (VCO), and a frequency divider, and an edge combiner. The PLL outputs a 12-phase clock by a VCO using six differential delay cells. The edge combiner synthesizes the frequency of the output clock through edge combining and frequency division of the 12-phase output clock of the PLL. The proposed PLL-based frequency synthesizer is designed using a 55-nm CMOS process with a 1.2-V supply voltage. It outputs three clocks with frequencies of 166 MHz, 83 MHz and 124.5MHz for a reference clock with a frequency of 20.75 MHz.

• Transactions on Semiconductor Engineering
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• v.2 no.3
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• pp.1-5
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• 2024

This paper presents a crystal-less reference clock recovery (CR) frequency synthesizer with compensation designed for Bluetooth Low Energy (BLE) Smart-tag applications, operating at frequencies of 32, 72, and 80MHz. In contrast to conventional frequency synthesizers, the proposed design eliminates the need for external components. Using a single-ended antenna to receive a minimal input power of -36dBm at a 2.4GHz signal, the CR synthesizes frequencies by processing the RF signal received through a Low Noise Amplifier ( L N A ) . This approach allows the system to generate a reference clock without relying on a crystal. The received signal is amplified by the LNA and then input to a 16-bit ACC (Automatic Clock Compensation) circuit. The ACC compares the frequency of the received signal with the oscillator output signal, using the synthesis of a 32MHz reference clock through a frequency compensation method. The oscillator is constructed using a Ring Oscillator (RO) with a Frequency Divider, offering three different frequencies (32/72/80MHz) for various system components. The proposed frequency synthesizer is implemented using a 55-nm CMOS process.

• Development and Reproduction
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• v.8 no.1
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• pp.57-64
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• 2004

This study was carried out to examine the expression of the circadian clock genes in the mouse ovary and testis at different developmental stages. Expression of Period1(Per 1), Period2(Per2), Period3(Per3), Cryptochrome1(Cry1), Cyptochrome2(Cry2), Clock Small and Prokineticin1 and Prokineticin2 receptor(Prok1r, Prok2r) genes in mouse ovary was explored by semiquantitative reverse transcription Polymerase chain reaction(RT-PCR) according to the developmental stage(post partum day; ppd 1, 7, 10, 21 and 35). Immunohistochemistry using PER1 antibody was also analyzed. The differential expression pattern of clock genes was presented according to stages of the mouse ovarian development (ppd 1, 7, 10, 21 and 35). In the cases of ovaries, at the starting point of follicle growth at ppd 7 and 10, the clock gene expression patterns were changed vastly. According to the developmental stages, the clock genes were highly expressed at ppd 7 and 10 in mouse testis also. Receptors for Prok2, the circadian output molecule of SCN, were also expressed in ovary at ppd 7 and in testis at ppd 1 and 7, respectively. Immnunohistochemical analysis of PER1 showed positive signals in the cytoplasm of oocytes and granulosa cells. The level or PER1 expression was increased in cells at the spermatogonia and the condensing spermatids. The expression pattern of Perl and localization of PER1 were showed similar patterns according to the developmental stages in ovary and testis. Taken together, it could be observed that the expression of clock genes was highly correlated with gonadal development and germ cell differentiation in mice. Therefore, in this study, circadian programming of the genes in the ovary and testis is strongly imposed across a wide range of core reproductive cycles and normal development of gametes. Although the existence of circadian genes is clearly investigated, further studies on the direct evidence is required for the understanding of the relationship between circadian genes and regulation of gonadal differentiation and germ cell development.

• The Journal of the Korea Contents Association
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• v.10 no.2
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• pp.72-80
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• 2010

The 1Gbps clock and data recovery (CDR) circuit using the proposed multi-point phase detector (PD) is presented. The proposed phase detector generates up/down signals comparing 3-point that is data transition point and clock rising/falling edge. The conventional PD uses the pulse width modulation (PWM) that controls the voltage controlled oscillator (VCO) using the width of a pulse period's multiple. However, the proposed PD uses the pulse number modulation (PNM) that regulates the VCO with the number of half clock cycle pulse. Therefore the proposed PD can controls VCO preciously and reduces the jitter. The CDR circuit is tested using 1Gbps $2^{31}-1$ pseudo random bit sequence (PRBS) input data. The designed CDR circuit shows that is capable of recovering clock and data at rates of 1Gbps. The recovered clock jitter is 7.36ps at 1GHz and the total power consumption is about 12mW. The proposed circuit is implemented using a 0.18um CMOS process under 1.8V supply.

• Reproductive and Developmental Biology
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• v.33 no.3
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• pp.163-169
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• 2009

Many biological systems are regulated by an intricate set of feedback loops that oscillate with a circadian rhythm of roughly 24 h. This circadian clock mediates an increase in body temperature, heart rate, blood pressure, and cortisol secretion early in the day. Recent studies have shown changes in the amplitude of the circadian clock in the hearts and livers of streptozotocin (STZ)-treated rats. It is therefore important to examine the relationships between circadian clock genes and growth factors and their effects on diabetic phenomena in animal models as well as in human patients. In this study, we sought to determine whether diurnal variation in organ development and the regulation of metabolism, including growth and development during the juvenile period in rats, exists as a mechanism for anticipating and responding to the environment. Also, we examined the relationship between changes in growth factor expression in the liver and clock-controlled protein synthesis and turnover, which are important in cellular growth. Specifically, we assessed the expression patterns of several clock genes, including Per1, Per2, Clock, Bmal1, Cry1 and Cry2 and growth factors such as insulin-like growth factor (IGF)-1 and -2 and transforming growth factor (TGF)-${\beta}1$ in rats with STZ-induced diabetes. Growth factor and clock gene expression in the liver at 1 week post-induction was clearly increased compared to the level in control rats. In contrast, the expression patterns of the genes were similar to those observed after 5 weeks in the STZ-treated rats. The increase in gene expression is likely a compensatory change in response to the obstruction of insulin function during the initial phase of induction. However, as the period of induction was extended, the expression of the compensatory genes decreased to the control level. This is likely the result of decreased insulin secretion due to the destruction of beta cells in the pancreas by STZ.