• The Mathematical Education
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• v.31 no.2
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• pp.93-107
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• 1992

The purpose of this study is to make out teaching-learning method for developing mathematical abilities of the 1st grade children in elementary school by investigating cognitive effects which mathematical pre-experiences given intentionally by teachers have on children's learning mathematics. The research questions for this purpose are as follows: In learning effects through mathematical pre-experiences given intentionally by teachers. 1) is there any differences between children with pre-experiences and children without them in Mathematics Achievement Test\ulcorner 2) is there any differences between children with pre-experiences and children without them in Transfer Test for learning effects\ulcorner For this study, a class with 41 children in H elementary school located in a Myon near Chong-ju was selected as an experimental group and a class with 43 children in G elementary school in the same Myon was selected as a control group. Nonequivalent Control Group Design of Quasi-Experimental Design was applied to this study. To give pre-experiences to the children in experimental group, their classroom was equipped with materials for pre-experiences, so children could always observe the materials and play with them. The materials were a round-clock on the wall, two pairs of scales, fifty dice, some small pebbles, two pairs of weight scales, two rulers on the wall, and various cards for playing games. Pre-experiences were given to the children repeatedly through games and observations during free time in the morning (00:20-09:00) and intervals between periods. There was a pretest for homogeneity of mathematics achievement between the two groups and were Mathematics Achievement Test (30 items) and Transfer Test (25 items) for learning effects as post-tests. The data were collected from the pretest on April 8 (control group), on April 11 (experimental group) and from the Mathematics Achievement Test and Transfer Test on July 15 (experimental group) and on July 16 (control group). T-test was used to analyze if there were any differences in the results of the test. The results of the analysis were as follows: (1) As the result of pretest, there was not a significance difference between the experimental group (M=17.10. SD=7.465) and the control group (M=16.31, SD=6.974) at p<.05 (p=0.632). (2) For the question 1. in the Mathematics Achievement Test, there was a significant difference between the experimental group (M=26.08, SD=4.827) and the control group (M=22.28. SD=5.913) at p<.01 (p=.003). (3) For the question 2. in the Transfer Test for learning effects. there was a significant difference between the experimental group (M=16.41, SD=5.800) and the control group (M=11.84, SD=4.815) at p<001, (p=.000). From the results of the analyses obtained in this study. the following conclusions can be drawn: First, mathematical pre-experiences given by teachers are effective in increasing mathematical achievement and transfer in learning mathematics. Second, games. observations, and experiments given intentionally by teachers can make children's mathematical experiences rich and various, and are effective in adjusting individual differences for the mathematical experiences obtained before they entered elementary schools. Third, it is necessary for teachers to give mathematical pre-experiences with close attention in order to stimulate children's mathematical interests and intellectual curiosity.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.4
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• pp.176-182
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• 2014

This paper introduces the development of global fringe search (GFS) software for preprocessing of Daejeon Correlator. In case of the VLBI observation, a observer conducts the observation for the reference sources with strong and point-like radio stars on schedule in order to confirm the well-observedness of the radio source by the radio telescope. The correlator performs the correlation for the reference sources to detect the fringe completely. We developed the GFS software by calculating the precise delay time between each observatory based on specific observatory. Then, this software calculates the precise delay time by using the delay model (correlator model) of reference source and information of time offset between the Hydrogen Maser frequency standard and GPS (Global Positioning System) clock located in each observatory through the correlation preprocessing. In order to confirm the performance of the developed software, experiments were carried out for the reference sources and target sources observed by the KaVA (KVN and VERA Array). Experimental results show that the GFS software has effectively good performance by finding the precise delay time offset according to the comparison between the compensated delay time offset and one without compensation.

• Korean Journal of Digital Imaging in Medicine
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• v.13 no.2
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• pp.63-69
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• 2011

Table strapis patient fixture for securing the patient movements and falls. if it designed to measure the abdominal circumference and used as an indicator of dose selection at CT scan. it will prevent the overexposure of dose without degradation of image quality and efficiently manage dose of each type of body to technician to deal with CT. First, in order to compare the dose used in CT image and qualitative characteristics. reference image is obtained by examining the abdominal phantom in same conditions with the hospital 120 kVp, 200 mAs, D-Dom (Dynamic Dose Of Modulation). SNR, PSNR, RMSE, MAE, CTDIvol of CT images are compared with reference image. for comparing with reference image, the image that Umbilicus level image of Abdomen CT is stored in the PACS were used. For comparison, the top 12 o'clock portion of the air drawn from the same ROI was measured. CTDIvol, mAs, etc. In order to analyze the characteristics of the image, by measuring the length of the umbilicus circumference, pattern of the dose was analyzed. by using the analyzed perimeter and dose information, To be identified visually, fixed band that scale marked were produced. Use them, If the length of circumference of less than 60 cm 100 mAs, Case of 61~80 cm 120 mAs, Case of 80~100 cm 150 mAs, more than 100 cm 200 mAs, dose selection based on the perimeter, the image was applied. by compare analyzed with the Reference Image, image quality was assessed. by compare with existing tests that equally 200 mAs applied, How much was confirmed that the dose reduction. 1. Depending on the Abdominal circumference, the average PSNR(dB) of the image that differently dose applied was 45.794. 2. Comparing with existing test. the dose of scan that adjusted the mAs depending on the circumference was decreased about 40%. SNR and PSNR of the image that obtained by adjusting the standard mAs based on dose modulation were not much different. Therefore, By choosing a low mAs. dose reduction can be obtained. and the dose selection method that measured Abdominal circumference using a fixed band can protect the overexposure and uniformly apply dose of each type of body to technician to deal with CT.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.62-74
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• 2008

In this paper, we would like to propose the design of symmetric digital filter core in order to use in the radio astronomy. The function of FIR filter core would be designed by VHDL code required at the Data Acquisition System (DAS) of Korean VLBI Network (KVN) based on the FPGA chip of Vertex-4 SX55 model of Xilinx company. The designed digital filter has the symmetric structure to increase the effectiveness of system by sharing the digital filter coefficient. The SFFU(Symmetric FIR Filter Unit) use the parallel processing method to perform the data processing efficiently by using the constrained system clock. In this paper, therefore, for the effective design of SFFU, the Unified Synthesis software ISE Foundation and Core Generator which has excellent GUI environment were used to overall IP core synthesis and experiments. Through the synthesis results of digital filter core, we verified the resource usage is less than 40% such as Slice LUT and achieved the maximum operation frequency is more than 260MHz. We also confirmed the SFFU would be well operated without error according to the SFFU simulation result using the Modelsim 6.1a of Mentor Graphics Company. To verify the function of SFFU, we carried out the additional simulation experiments using the pseudo signal to the Matlab software. From the comparison experimental results of simulation and the designed digital FIR filter, we confirmed the FIR filter was well performed with filter's basic function. So we verified the effectiveness of the designed FIR digital filter with symmetric structure using FPGA and VHDL.

• Journal of the East Asian Society of Dietary Life
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• v.14 no.5
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• pp.397-406
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• 2004

The purpose of this study was to analyze women's consumption and preferences of the Korean traditional drinks. For this purpose, 205 women aged between teens and 60s living in Seoul were sampled randomly for a questionnaire survey conducted from August 21 to 27, 2003. The results of this study were summarized as follows: The percentile of age groups accounted for 15.6% of the subjects in their teens, 19.5% in 20s, 18.0% in 30s, 20.5% in 40s, 13.7% in 50s, and 12.7% in 60s, respectively. On the other hand, those who graduated from colleges accounted for most (49.8%) of the subjects, those employed by companies for most (23.9%) and those earning 2 million wons or more for most (40.5%). Subjects' preferences about the traditional drinks were as follows: The most popular traditional drink across all age groups was Sikhe (29.8%: fermented rice drink), followed by Sujonggwa (10.7%: dried persimmons punch) and green tea (8.8%). Most of those in their teens and 60s consumed the drinks to relieve from the thirst, while those between 20s and 50s to be healthy. The majority (31.7%) of the subjects were consuming the traditional drinks once or twice per week. Those in their teens and 40s consumed the drinks between 3 and 5 o'clock in the afternoon, while those in their 20s, 30s and 50s as they want, and those in their 60s after exercise and as they pleased. 63.4% of the subjects across all age groups bought the drinks at supermarkets, and 60.5% of them were consuming 200ml each time. The reasons of subjects' preferences of the traditional drinks were as follows: The most important factor perceived by all age groups was taste (61.0%), followed by nutrition (15.6%). The most preferred point of taste was 'light' (51.7%). Those in their teens preferred the drinks without grains, while the other age groups preferred the drinks with some grains. Those in their teens preferred canned drinks, while the other age groups preferred the bottled drinks. Consumers' desire for improvement of traditional drinks were as follows: Those in their teens and 20s were satisfied with the current prices of the drinks, while the other age groups hoped for lower prices. On the other hand, those in their 50s answered that the drinks should not be sweet, while the other age groups hoped that the tastes of the drinks would be improved in diverse ways. 53.2% of the consumers hoped that the flavors of the traditional drinks would be diversified. 67.3% of them hoped that the traditional drinks would be improved to be functional drinks, while 54.6% of them hoped that the drinks would be processed in a more hygienic way.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.47-52
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• 2006

This paper proposes a novel low-power $32bit\times32bit$ multiplier for deep submicron technologies beyond 130nm. As technology becomes small, static power due to leakage current significantly increases, and it becomes comparable to dynamic power. Recently, shutdown method based on MTCMOS is widely used to reduce both dynamic and static power. However, it suffers from severe power line noise when restoring whole large-size functional block. Therefore, the proposed multiplier mitigates this noise by shutting down and waking up sequentially along with pipeline stage. Fabricated chip measurement results in $0.35{\mu}m$ technology and gate-transition-level simulation results in 130nm and 90nm technologies show that it consumes $66{\mu}W,\;13{\mu}W,\;and\;6{\mu}W$ in idle mode, respectively, and it reduces power consumption to $0.04%\sim0.08%$ of active mode. As technology becomes small, power reduction efficiency degrades in the conventional clock gating scheme, but the proposed multiplier does not.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.60-69
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer(PADFE) using a 0.25-${\mu}m$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of the ADFE by using delayed least-mean-square(DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width, and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The single-chip PADFE contains about 205,000 transistors on an area of about $1.96\times1.35-mm^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW. Test results show that the fabricated chip works functionally well.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.6
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• pp.18-24
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• 2012

This paper reports the test results of a 50MHz/s 10 bits DAC developed with $0.18{\mu}m$ CMOS process for the wireless sensor network application. The 10bits DAC, not likely a typical segmented type, has been designed as a current driving type with double step thermometer decoding architecture in which 10bits are divided into 6bits of MSB and 4bits of LSB. MSB 6bits are converted into 3 bits row thermal codes and 3 bits column thermal codes to control high current cells, and LSB 4 bits are also converted into thermal codes to control the lower current cells. The high and the lower current cells use the same cell size while a bias circuit has been designed to make the amount of lower unit current become 1/16 of high unit current. All thermal codes are synchronized with output latches to prevent glitches on the output signals. The test results show that the DAC consumes 4.3mA DC current with 3.3V DC supply for 2.2Vpp output at 50MHz clock. The linearity characteristics of DAC are the maximum SFDR of 62.02dB, maximum DNL of 0.37 LSB, and maximum INL of 0.67 LSB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.50-55
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• 2008

In this paper, New LC VCO with $8{\sim}10.9$ GHz Band has been designed using commercial $0.35-{\mu}m$ CMOS technology. This proposed circuit is consisted of the parallel construction of the typical NMOS and PMOS cross-coupled pair which is based on the LC tank, MOS cross-coupled pair which has same tail current of complementary NMOS and PMOS, and output buffer. The designed LC VCO, which is according to proposed structure in this paper, takes a 29% improvement of the wide tuning range as 8 GHz to 10.9 GHz, and a 6.48mW of low power dissipation. Its core size is $270{\mu}m{\times}340{\mu}m$ and its phase noise is as -117dBc Hz and -137dBc Hz at 1-MHz and 10-MHz offset, respectively. FOM of the new proposed LC VCO gets -189dBc/Hz at a 1-MHz offset from a 10GHz center frequency. This design is very useful for the 10Gb/s clock generator and data recovery integrated circuit(IC) and SONET communication applications.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.78-89
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• 2013

This paper proposes a high-throughput and multi-mode quasi-cyclic (QC) low-density parity-check (LDPC) decoder based on a fully parallel structure. The proposed QC-LDPC decoder employs the fully parallel structure to provide very high throughput. The high interconnection complexity, which is the general problem in the fully parallel structure, is solved by using a broadcasting-based sum-product algorithm and proposing a low-complexity cyclic shift network. The high complexity problem, which is caused by using a large amount of check node processors and variable node processors, is solved by proposing a combined check and variable node processor (CCVP). The proposed QC-LDPC decoder can support the multi-mode decoding by proposing a routing-based interconnection network, the flexible CCVP and the flexible cyclic shift network. The proposed QC-LDPC decoder is operated at 100 MHz clock frequency. The proposed QC-LDPC decoder supports multi-mode decoding and provides 8.1 Gbps throughput for a (1944, 1620) QC-LDPC code.