• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.5 s.335
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• pp.13-22
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• 2005

IEEE 802.11a is a standard for the high-speed wireless local area network (WLAN), supporting from 6 up to 54 Mbps in a 5 GHz band. We propose a channel equalization algerian and a sampling clock recovery algorithm by utilizing the Viterbi decoder output of the IEEE 802.11a WLAN standard. The proposed channel equalizer adaptively compensates channel variations. The proposed system uses re-encoded Viterbi decoder outputs as reference symbols for the adaptation of the channel equalizer. It also extracts sampling phase information with the Viterbi decoder outputs for fine adjustment of the sampling clock. The proposed sampling clock recovery and equalizer are more robust to noise and frequency selective fading environments than conventional systems using only four pilot samples.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.232-239
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• 2010

By using the clock timing control at transmitter (TX), the crosstalk-induced jitter (CIJ) is compensated for in the 2-bit parallel data transmission through the coupled microstrip lines on printed circuit board (PCB). Compared to the authors' prior work, the delay block circuit is simplified by combining a delay block with a minimal number of stages and a 3-to-1 multiplexer. The delay block generates three clock signals with different delays corresponding to the channel delay of three different signal modes. The 3-to-1 multiplexer selects one of the three clock signals for TX timing depending on the signal mode. The TX is implemented by using a $0.18\;{\mu}m$ CMOS process. The measurement shows that the TX reduces the RX jitters by about 38 ps at the data rates from 2.6 Gbps to 3.8 Gbps. Compared to the authors' prior work, the amount of RX Jitter reduction increases from 28 ps to 38 ps by using the improved implementation.

• Journal of Astronomy and Space Sciences
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• v.28 no.1
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• pp.79-91
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• 2011

Ongnu (Jade Clepsydra; also called Heumgyeonggaknu) is a water clock was made by Jang Yeong-sil in 1438. It is not only an automatic water clock that makes the sound at every hour on the hour by striking bell, drum and gong, but also an astronomical clock that shows the sun's movement over time. Ongnu's power mechanism used is a water-hammering method applied to automatic time-signal device. The appearance of Ongnu is modeled by Gasan (pasted-paper imitation mountain) and Binpungdo (landscape of farming work scene) is drawn at the foot of the mountain. The structure of Ongnu is divided into the top of the mountain, the foot of the mountain and the flatland. There located are sun-movement device, Ongnyeo (jade female immortal; I) and Four gods (shaped of animal-like immortals) at the top of the mountain, Sasin (jack hour) and Musa (warrior) at the foot of the mountain, and Twelve gods, Ongnyeo (II) and Gwanin on the flatland. In this study, we clearly and systematically understood the time-announcing mechanism of each puppet. Also, we showed the working mechanism of the sun-movement device. Finally, we completely established the 3D model of Ongnu based on this study.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.5
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• pp.1104-1109
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• 2015

Due to the rapid growth in digital contents, it is important for us to design a high speed and secure encryption algorithm which is able to comply with the existing and future needs. This paper proposes an alternative approach for self-decimated LM-128 summation sequence generator, which will generate a higher throughput if compared to the conventional generator. We design and implement a threshold clock-controlled LM-128 and prove that it has a lower clock cycle and hence giving a higher key stream generation speed. The proposed threshold clock-control LM-128 generator consists of 256 bits inner state with 128 bits secret key and initialization vector. The cipher achieves a security level of 128 bits to be adapted to the digital contents security with high definition and high quality.

• Proceedings of the KIPE Conference
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• 2004.07a
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• pp.97-100
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• 2004

Our country has depended on fossil fuel very much according to the Increasing of the demand of the electric power. For instance, if the reduction and freezing caused by the warm gas in earth by the regulation of international environment happen in Korea it will bring about the result of weakness in industrial activity. As a result, it will cause many problems to compete an advanced country which wants to connect environment with the activity of industrial product in their country. The photovoltaic system outputs have peak about a half past 13 o'clock(before and after) mainly in a good weather. The output decreases rapidly from a half past 17 o'clock and PV output doesn't work at six o'clock before the sun rises. The outputs of PV system stops at that time. The frequent degree of harmonics in dwelling house which lots of people live has peak from 19 o'clock to 22 o'clock Harmonics mainly happens at least at night. In recent, many researches about power quality has been studying very hard in order to solve the question, the voltage fluctuating and harmonics as one compensator. In this paper, I suggest the algorithm which can increase the power quality as a rate of operation of this system. This algorithm proves to have effectiveness through computer simulation.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.56-63
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• 2015

Not only performance analysis but also power analysis at early design stages is important in designing a system-on-chip. We propose a power modeling based on clock gating enable signals that enables accurate power analysis at a high-level. Power state is defined as combinations of the values of the clock gating enable signals and we can extract the clock gating enable signals to generate the power model automatically. Experimental results show that the average power accuracy is about 96% and the speed gain of power analysis at the high-level power is about 280 times compared to that at the gate-level.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.568-576
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• 2017

This paper presents a clock and data recovery circuit with an adaptive loop bandwidth calibration scheme and the idle power saved frequency acquisition. The loop bandwidth calibration adaptively controls injection currents of the main loop with a trimmable bandgap reference circuit and trains the VCO to operate in the linear frequency control range. For stand-by power reduction of the phase detector, a clock gating circuit blocks 8-phase clock signals from the VCO and cuts off the current paths of current mode D-flip flops and latches during the frequency acquisition. 77.96% reduction has been accomplished in idle power consumption of the phase detector. In the jitter experiment, the proposed scheme reduces the jitter tolerance variation from 0.45-UI to 0.2-UI at 1-MHz as compared with the conventional circuit.

• Interdisciplinary Bio Central
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• v.1 no.1
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• pp.5.1-5.4
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• 2009

This article is an addendum to the authors’ previous article (Kim, J. et al. (2008) Plant Cell 20, 307-319). The instrumentation and software described in this article were used to analyze the circadian leaf movement in the previous article. Here, we provide detailed and practical information on the instrumentation and the software. The source code of the LMA program is freely available from the authors. The circadian clock regulates a wide range of cyclic physiological responses with a 24 hour period in most organisms. Rhythmic leaf movement in plants is a typical robust manifestation of rhythms controlled by the circadian clock and has been used to monitor endogenous circadian clock activity. Here, we introduce a relatively easy, inexpensive, and simple approach for measuring leaf movement circadian rhythms using a USB-based web camera, public domain software and a Leaf Movement Assay (LMA) program. The LMA program is a semi-automated tool that enables the user to measure leaf lengths of individual Arabidopsis seedlings from a set of time-series images and generates a wave-form output for leaf rhythm. This is a useful and convenient tool for monitoring the status of a plant's circadian clock without an expensive commercial instrumentation and software.

• Animal cells and systems
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• v.13 no.2
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• pp.119-125
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• 2009

Mammalian hibernation is a type of natural adaptation that allows organisms to avoid harsh environment and to increase the possibility of survival. To investigate the molecular link between circadian and hibernating rhythms in the greater tube-nosed bats, Murina leucogaster, we set out to identify circadian genes that are expressed in bats, with specific focus on the PAS domain by using PCR-based screens. We could isolate a eDNA clone, designated as LPAS1, that encodes a protein of 521 amino acid residues. LPAS1 is closely related with CLOCK family with the highest homology to human CLOCK. Based on RT-PCR analyses, LPAS1 transcripts are ubiquitously present in tissues from both summer active and winter dormant periods. Given that LPAS1 is a member of the bHLH-PAS protein superfamily but lacks polyglutamine transactivation domains, it is likely to function as a repressor for endogenous CLOCK to hinder its roles in promoting transcription. Our result will open a new avenue to further examine the functional interconnection between the circadian clock and the circannual clock such as mammalian hibernation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.9A
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• pp.868-877
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• 2006

Sensor network applications need synchronized time to the highest degree such as object tracking, consistent state updates, duplicate detection, and temporal order delivery. In addition, reliability issues and fault tolerance in sophisticated sensor networks have become a critical area of research today. In this paper, we proposed a fault tolerant clock management scheme in sensor networks considering two cases of fault model such as network faults and clock faults. The proposed scheme restricts the propagation of synchronization error when there are clock faults of nodes such as rapid fluctuation, severe changes in drift rate, and so on. In addition, it handles topology changes. Simulation results show that the proposed method has about $1.5{\sim}2.0$ times better performance than TPSN in the presence of faults.