• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.6 s.121
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• pp.584-590
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• 2007

In this paper, the efficiency of power amplifier has been maximized by the application of EER structure, and the linearity has been improved by using PBG structure. This paper has proposed a design of power amplifier in class-F to get the PAE, and to control dynamic power using envelope detector. PBG structure gets high-linearity by removing harmonics arisen from the mismatching of matching circuit. The PAE and the 3rd order IMD have been improved 34.64%, 6.65 dB compared with those of conventional Doherty amplifier, respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.2
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• pp.72-75
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• 2012

In this paper, high-efficiency DC-AC converter is implemented for the wireless power transmission. The DC-AC converter is implemented by combining the oscillator and power amplifier. Because the conversion efficiency of wireless power transmitter is strongly affected by the efficiency of power amplifier, the high-efficiency power amplifier is implemented by using the Class-E amplifier structure. Also, because the output power of oscillator connected to the input stage of power amplifier is low, high-gain two-stages power amplifier using the drive amplifier is implemented to realize the high-output power DC-AC converter. The dual band harmonic suppression filter is implemented to suppress 2nd, 3rd harmonics of 13.56 MHz. The output power and conversion efficiency of DC-AC converter are 40 dBm and 80.2 % at the operation frequency of 13.56 MHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.9
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• pp.987-994
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• 2010

In this paper, a simple and effective active load-pull method is proposed, and the method to improve the efficiency of X-band power amplifier using harmonic control circuit is presented. The proposed active load-pull system mainly consists of directional coupler, phase shifter, short circuit, and power amplifier, and allows a user to access reflection coefficients near the edge of the Smith chart($\Gamma$=1) easily. The device used in this paper is Mitsubishi's GaAs FET MGF1801, and the operating frequency of the power amplifier is 9 GHz, The amplifier had output power of 21.65 dBm and drain efficiency of 24.9 % at class-A, and had output power of 21.46 dBm and drain efficiency of 53.3 % at class-AB. Harmonic control circuit is designed only second and third harmonic components because of the bandwidth limitation of the microwave components. The drain efficiency is improved as much as 6.4 % compared with class-AB power amplifier.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.8 no.2
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• pp.75-82
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• 2009

This paper proposes a method which increases the linearity using an improvement mechanism of Doherty power amplifier and compensates the decrement of efficiency due to improvement of linearity. To verify the method, a 20W power amplifier is designed and implemented. Compared with 2-way Doherty power amplifier, the implemented 3-way Doherty power amplifier with class F shows improved linearity about 10dBc and efficiency about 1.5%. Also, efficiency characteristic has been improved about 3.5% compared with the 2-way Doherty power amplifier while maintaining linearity. This results show that the proposed 3-way Doherty power amplifier with class F is shown to be adequate for improvement of efficiency and linearity. It is expected that the proposed amplifier can be used for various wireless communication system amplifiers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.44-51
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• 2008

A stereo audio digital-to-analog converter (DAC) with a power amplifier using asymmetric pulse-width modulation (PWM) is presented. To adopt class-D amplifier mainly used in high-power audio appliances for head-phones application, this work analyzes the noise caused by the inter-channel interference during the integration and optimizes the design of the sigma-delta modulator to decrease the performance degradation caused by the noise. The asymmetric PWM is implemented to reduce switching noise and power loss generated from the power amplifier. This proposed architecture is fabricated in 0.13-mm CMOS technology. The proposed audio DAC including the power amplifier with single-ended output achieves a dynamic range (DR) of 95-dB dissipating 4.4-mW.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.9 no.5
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• pp.72-79
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• 2010

In this paper, we describe the design and implementation of a high efficiency Doherty power amplifier using gallium nitride (GaN) high-electron mobility transistor (HEMT). The carrier and peaking amplifiers of the proposed Doherty power amplifier consist of the switching-mode Class-E power amplifiers. The test conditions are a duty of 10% and a pulse width of $100\;{\mu}s$ and pulse repetition frequency (PRF) of 1 kHz for a S-band radar application. A RF performance peak PAE of 64% with drain efficiency of 80.6%, at 6 dB output back-off point from saturated output power of 45.5 dBm, was obtained at 2.85 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.6
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• pp.613-622
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• 2013

In this paper, an inductive clamping class-E power amplifier has been tested for wireless power transmission at ISM band, 13.56 MHz. The implemented power amplifier is designed to operate stably without destroying power transistor in wireless power transmission system which basically keeps not to align between a transmitting antenna and a receiving antenna. The power amplifier is also designed to enhance harmonic filtering characteristic. The amplifier was tested with a DC supply voltage of 28 V and input power of 25 dBm at 13.56 MHz. The test results show the output power level of 43 dBm, the difference power level between fundamental frequency and second harmonic frequency of more than 55 dBc, the dc current consumption of 830 mA, and the high power-added efficiency of 85 %. Finally, the implemented power amplifier operated normally with 830 mA DC current consumption from 28 V source when the two antennas were aligned, and the power transmission was successful. But when the two antennas were not aligned, its DC current consumption automatically decreased down to 420 mA to protect the switching transistor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.44-53
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• 2008

In this paper, we present the design of delta-sigma modulation-based class-D amplifier for driving headphones in portable audio applications. The presented class-D amplifier generates PWM(pulse width modulation) signals using a single-bit fourth-order high-performance delta-sigma modulator. To achieve a high SNR(signal-to-noise ratio) and ensure system stability, the locations of the modulator loop filter poles and zeros are optimized and thoroughly simulated. The test chip is fabricated using a standard $0.18{\mu}m$ CMOS process. The active area of the chip is $1.6mm^2$. It operates for the signal bandwidth from 20Hz to 20kHz. The measured THD+N(total harmonic distortion plus noise) at the $32{\Omega}$ load terminal is less than 0.03% from a 3V power supply.

• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2704-2707
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• 1999

This paper presents a simple high power audio class amplifier which is controlled by a new current control switching method. Although this class D amplifier has an only one current control loop with the proposed switching method, a good performance can be obtained. And a novel switching strategy for driving stereo signal amplifier circuit with three phase full bridge is discussed also. With the simulation and experimental results, usefulness of the proposed amplifier is confirmed.

• Journal of electromagnetic engineering and science
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• v.14 no.3
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• pp.284-292
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• 2014

This paper presents a characteristic evaluation of commercial gallium nitride (GaN) transistors having two different gate-lengths of $0.4-{\mu}m$ and $0.25-{\mu}m$ in the design of a class-S power amplifier (PA). Class-S PA is operated by a random pulse-width input signal from band-pass delta-sigma modulation and has to deal with harmonics that consider quantization noise. Although a transistor having a short gate-length has an advantage of efficient operation at higher frequency for harmonics of the pulse signal, several problems can arise, such as the cost and export license of a $0.25-{\mu}m$ transistor. The possibility of using a $0.4-{\mu}m$ transistor on a class-S PA at 955 MHz is evaluated by comparing the frequency characteristics of GaN transistors having two different gate-lengths and extracting the intrinsic parameters as a shape of the simplified switch-based model. In addition, the effectiveness of the switch model is evaluated by currentmode class-D (CMCD) simulation. Finally, device characteristics are compared in terms of current-mode class-S PA. The analyses of the CMCD PA reveal that although the efficiency of $0.4-{\mu}m$ transistor decreases more as the operating frequency increases from 955 MHz to 3,500 MHz due to the efficiency limitation at the higher frequency region, it shows similar power and efficiency of 41.6 dBm and 49%, respectively, at 955 MHz when compared to the $0.25-{\mu}m$ transistor.