• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.905-908
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• 2005

본 논문에서는 class AB opamp 를 채용한 384kHz differential PWM 신호를 입력으로 하는 2-channel stereo audio amplifier 블록을 공급전압 3.3V 조건에서 SMIC 0.18um thick oxide 기술을 이용하여 설계한다. 여기서 class AB opamp 는 공정 변화에 따른 quiescent current가 변하는 것을 최소화하기 위하여 adaptive load 를 사용하며, 전체적으로는 3 차 Butterworth lowpass filter 와 differential-to-single converter 로 구성된 2 개의 audio amplifier 와 출력전압이 ${\frac{1}{2}}Vdd$ 인 common output 블록으로 구성된다. 이러한 설계를 통하여 32ohm 의 저항 load 를 구동할 수 있는 -60dB THD, 전체 quiescent current 2mA 대인 CMOS class AB stereo audio amplifier 를 구현하였다.

• Journal of Advanced Navigation Technology
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• v.23 no.2
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• pp.166-171
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• 2019

This paper has designed a current mode class D power amplifier to increase the transmission efficiency of a 6.78 MHz wireless power transfer (WPT) transmitter and to ensure stable characteristics even when the transmitting and receiving coil intervals change. By reducing the loss due to the parasitic capacitor component of the transistor, which limits the theoretical efficiency of the linear amplifier, this research has improved the efficiency of the power amplifier. The circuit design simulator was used to design the high efficiency amplifier, and the power output and efficiency characteristics according to the load impedance change have been simulated and verified. In the simulation, 42.1 dBm output and 95% efficiency was designed at DC bias 30 V. The power amplifier was fabricated and showed 91% efficiency at the output of 42.1 dBm (16 W). The transmitting and receiving coils were fabricated for wireless power transfer of the drone, and the maximum power added efficiency was 88% and the output power was $42.1dBm{\pm}1.7dB$ according to the load change causing from the coil intervals.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.43-46
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• 2012

In this paper, high efficiency power amplifier is implemented with high gain amplifier. Two-stage amplifier using adaptive bias control circuit improve efficiency at low input power. Fixed bias circuit and adaptive bias circuit both have about 76 % efficiency at maximum power level. However amplifier using an adaptive bias control circuit has 70 % at 6 dBm input power level when the amplifier using fixed bias circuit has 50%. The proposed power amplifier using the adaptive bias control circuit can have high efficiency at lower power level.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.12
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• pp.1060-1068
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• 2011

In this paper, Current-Mode Class-D(CMCD) RF Power Amplifier(PA) is designed and implemented at 900 MHz. Conventional CMCD PA has output parallel resonator to reconstruct a fundamental frequency component of the output signal. However the resonator can be removed by connecting inverse class-F PAs because even-harmonic components can be removed by CMCD PA's push-pull structure. Using load-pull, inverse class-F PA with GaN transistors is designed, and CMCD PA with the inverse class-F PA is implemented. The CMCD PA has 64.5 % drain efficiency, 34.2 dBm output power. Comparing with the drain efficiency of a CMCD PA with parallel resonator, the CMCD with the inverse class-F technology has 13.6 % improved drain efficiency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.5
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• pp.624-631
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• 2012

This paper presents a high-efficiency current mode class-D(CMCD) power amplifier for the 13.56 MHz band using a Guanella's 1:1 transmission-line transformer and filtering circuits at the output network. The second and third s are filtered out in the load network of the class-D amplifier. The implemented CMCD power amplifier exhibited a power gain of 13.4 dB and a high power-added efficiency(PAE) of 84.6 % at an output power of 44.4 dBm using the 13.56 MHz CW input signal. The second and third distortion levels were -50.3 dBc and -46.4 dBc at the same output power level, respectively.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.10 no.5
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• pp.71-78
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• 2011

In this paper, we describe the design and implementation of a high efficiency and broad-band Class-J mode power amplifier using gallium nitride(GaN) high-electron mobility transistor(HEMT). The matching circuit of proposed class-J mode power amplifier for 2nd harmonic impedance designed to provide pure reactance alone. The measurement results show that output power of $40{\pm}1$ dBm, power-added efficiency of 50%, and drain efficiency of 60% for a continuous wave signal at 1.4 to 2.6 GHz.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.499-502
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• 2004

A two-stage Class E power amplifier operated at 2.44GHz is designed in 0.25-$\mu$m CMOS process for Class-l Bluetooth application. The power amplifier employs c1ass-E topology to exploit its soft-switching property for high efficiency. A preamplifter with common-mode configuration is used to drive the output-stage of Class-E type. The amplifier delivers 20-dBm output power with 70$\%$ PAE (power -added-efficiency) at 2-V supply voltage.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2007.05a
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• pp.400-403
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• 2007

This research describes how the class D amplifiers with power efficiency are designed and implemented for the PA audio systems. The configuration that makes use of the class D amplifier properties depends strongly on their applications. Thus in this paper the characteristics of the 2-level and 3-level PWM are analysed and the circuit implementation for them is presented. Using the proposed methods, they are designed and simulated for the further investigation. Test(Simulation) results present the improved performance that shows the satisfactory operations in controlling the PWM to the input signals.

• Proceedings of the KIEE Conference
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• 1994.11a
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• pp.141-143
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• 1994

The pulse width modulated class D power amplifier has the highest efficiency among various class amplifiers but the performances, such as bandwidth, distortion and stability are inferior to the conventional ones. In this paper, a new class D amplifier design is Presented employing dual feedback loops namely current and voltage feedback. The new design provides wide full-power bandwidth and stability at any load with high efficiency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.1
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• pp.114-121
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• 2003

In this paper, low voltage and two stage CMOS Class E RF power amplifier for ISM(Industrial/Scientific/Medical) Open Band is presented. The power amplifier operates at 2.4GHz frequency, and is designed and simulated with a 0.35um CMOS technology and HSPICE simulator. The power amplifier is simple structure of two stage Class E power amplifier. The design procedure determing matching network was presented. The power amplifier is composed of input stage matching network, preamplifier, interstage matching network, power amplifier, and output stage matching network. The matching networks of input stage and interstage were constituted by pi($\pi$) type and L type respectively. At 2.4GHz operating frequency, and with a 2.5V supply voltage, the power amplifier delivers 23dBm output power to a 50${\Omega}$ load with 39% power added efficiency(PAE).