• Journal of Power Electronics
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• v.14 no.4
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• pp.641-648
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• 2014

This paper presents the design considerations and analysis for an interleaved boundary conduction mode power factor correction buck converter. A thorough analysis of the harmonic content of the AC line current is presented to examine the allowable voltage gain (K value) for meeting the EN61000-3-2, Class D standard while maximizing efficiency. The results of the harmonic analysis are used to derive the required value of K and therefore the output voltage necessary to meet the class D requirements for a given AC line voltage. The discussed design consideration and harmonic current analysis are verified on a 300W universal line experimental prototype converter with an 80V output. The measured efficiencies remain above 96% down to 20% of the full load. The input current harmonics also meet the IEC61000-3-2 (class D) standard.

• Journal of electromagnetic engineering and science
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• v.11 no.3
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• pp.161-165
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• 2011

In this paper, a high-efficiency DC-AC converter is used for wireless energy transmission. The DC-AC convertter is implemented by combining the oscillator and power amplifier. Given that the conversion efficiency of a DC-AC converter is strongly affected by the efficiency of the power amplifier, a high-efficiency power amplifier is implemented using a class-E amplifier structure. Also, because of the low output power of the oscillator connected to the input stage of the power amplifier, a high-gain two-stage power amplifier using a drive amplifier is used to realize a high-output power DC-AC converter. The high-efficiency DC-AC converter is realized by connecting the oscillator to the input stage of the high-gain high-efficiency two-stage class-E power amplifier. The output power and the conversion efficiency of the DC-AC converter are 40.83 dBm and 87.32 %, respectively, at an operation frequency of 13.56 MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.149-156
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• 2012

A digital input class-D audio amplifier is presented for digital hearing aid. The class-D audio amplifier is composed of digital and analog circuits. The analog circuit converts a digital input to a analog audio signal (DAC) with noise suppression in the audio band. An interpolated digital delta-sigma modulator is used to convert data types between digital signal processor (DSP) and digital-to-analog converter (DAC). An 16-bit, 25-kbps pulse code modulated (PCM) input is interpolated to 16-bit, 50-kbps by a digital filter. The output signal of interpolation filter is noise-shaped by a third-order digital sigma-delta modulator (SDM). As a result, 1.5-bit, 3.2-Mbps signal is applied to simple digital to analog converter.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.2
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• pp.72-75
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• 2012

In this paper, high-efficiency DC-AC converter is implemented for the wireless power transmission. The DC-AC converter is implemented by combining the oscillator and power amplifier. Because the conversion efficiency of wireless power transmitter is strongly affected by the efficiency of power amplifier, the high-efficiency power amplifier is implemented by using the Class-E amplifier structure. Also, because the output power of oscillator connected to the input stage of power amplifier is low, high-gain two-stages power amplifier using the drive amplifier is implemented to realize the high-output power DC-AC converter. The dual band harmonic suppression filter is implemented to suppress 2nd, 3rd harmonics of 13.56 MHz. The output power and conversion efficiency of DC-AC converter are 40 dBm and 80.2 % at the operation frequency of 13.56 MHz.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.2
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• pp.267-272
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• 2017

In this paper, we suggested that a RF-front module of down-converter that represents the lowest noise figure to receive high quality video signals because the attenuation occurs in the atmosphere over 20GHz. By budget analysis of CDR, SFDR and CIP3 of RF-FEM, we also analyzed the parameters and linearity that presents high dynamic range. The total gain of designed Ka-band down-converter is 61.8dBand noise figure is 1.05dB, so gain and noise figures show excellent properties. In the future, the designed RF-FEM will be applied to the Ka-band satellite down-converter for UHD-class video transmission.

• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.288-294
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• 2015

Recently, the module-integrated converter has shown an interest in the photovoltaic generation system. In this system, the high frequency transformer should be compact and efficient. The proposed method is based on the correlation characteristic between the copper and core loss to minimize the loss of transformer. By sizing an effective cross-sectional area and window area of core, the amount of loss is minimized. This paper presents the design and analysis of high frequency transformer by using the 3D finite element model coupled with DC-DC converter circuit for more accurate analysis by considering the nonlinear voltage and current waveforms in converter circuit. The current waveform in each winding is realized by using the ideal DC voltage source and switching component. And, the thermal analysis is performed to satisfy the electrical and thermal design criteria.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.5
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• pp.335-342
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• 2022

In this paper, a single-bit 3rd-order feedforward delta sigma modulator is proposed for audio applications. The proposed modulator is based on a class-C inverter for low voltage and power applications. For the high-precision requirement, the class-C inverter with regulated cascode structure increases its DC gain and acts as a low-voltage subthreshold amplifier. The proposed Class-C inverter-based modulator is designed and simulated in 180-nm CMOS process. With no performance loss and a low supply voltage compatibility, the proposed class-C inverter-based switched-capacitor modulator achieves high power efficiency. This design achieves an signal-to-noise-and-distortion ratio (SNDR) of 93.9 dB, an signal-to-noise ratio (SNR) of 108 dB, an spurious-free dynamic range (SFDR) of 102 dB, and a dynamic range (DR) of 102 dB at a signal bandwidth of 20 kHz and a sampling frequency of 4 MHz, while only using 280 μW of power consumption from a 0.8-V power supply.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1725-1734
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• 2016

This paper presents a novel seven-level (7L) voltage source converter for high-power medium-voltage applications. The proposed topology is an H-bridge connection of two nested neutral-point clamped (NNPC) converters and is referred to as an HNNPC converter. This converter exhibits advantageous features, such as operating over a wide range of output voltages, particularly for 10-15 kV applications, without the need to connect power semiconductors in series; high-quality output voltage; and fewer components relative to other classic seven-level topologies. A novel sinusoidal pulse width modulation technique is also developed for the proposed 7L-HNNPC converter to control flying capacitor voltages. One of the main features of the control strategy is the independent application of control to each arm of the converter to significantly reduce the complexity of the controller. The performance of the proposed converter is studied under different operating conditions via MATLAB/Simulink simulation, and its feasibility is evaluated experimentally on a scaled-down prototype converter.

• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.1
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• pp.18-29
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• 2002

Generally, the single-stage power factor corrected converter has a problem of high dc link voltage. In the case of high line voltage, especially, the dc link voltage is verb high under the light load condition. To solve this problem, a new single stage power factor corrected AC/DC converter has been proposed. The proposed converter has huck topology as a power factor corrector. To prove feasibility of the proposed converter, the design example of the proposed converter has been presented. The design considerations and experimental results for the proposed converter have been shown. The experimental results show that the line input current harmonics can meet IEC1000-3-2 Class D requirements for the range of line input voltage from 90Vrms to 260Vrms.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.905-908
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• 2005

본 논문에서는 class AB opamp 를 채용한 384kHz differential PWM 신호를 입력으로 하는 2-channel stereo audio amplifier 블록을 공급전압 3.3V 조건에서 SMIC 0.18um thick oxide 기술을 이용하여 설계한다. 여기서 class AB opamp 는 공정 변화에 따른 quiescent current가 변하는 것을 최소화하기 위하여 adaptive load 를 사용하며, 전체적으로는 3 차 Butterworth lowpass filter 와 differential-to-single converter 로 구성된 2 개의 audio amplifier 와 출력전압이 ${\frac{1}{2}}Vdd$ 인 common output 블록으로 구성된다. 이러한 설계를 통하여 32ohm 의 저항 load 를 구동할 수 있는 -60dB THD, 전체 quiescent current 2mA 대인 CMOS class AB stereo audio amplifier 를 구현하였다.