• 한국조명전기설비학회지:조명전기설비
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• 제9권5호
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• pp.51-56
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• 1995

The transistors of single phase 3 level PWM Inverter compose output power transistors and neutral point clamping transistors, which are NPN transistors. Waveforms of driving signals for this are PWM waves for power transistors and period operating waves for neutral point clamping transistors, which signals made W-type modulation from rectangular and sine wave. The output power transistors operate at ON-time complementary and neutral point clamping transistors operate at OFF-time complementary respectively. Therefore, each transistors operate in half period at parallel. Characteristics of this inverter circuit is parallel switching method about series switching method of general inverter. As modulation of 3 level drive signals made from full-wave rectifier of sine wave and rectangular wave, which are level wave about 3 level of complementary transistor inverter. So, this circuit composed complementary operation inverter of NPN transistors only compare with PNP-NPN complementary inverter, which have high power 3 level inverter of complementary operation.

• 한국자기학회지
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• 제26권2호
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• pp.55-61
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• 2016

본 논문에서는 설계변수 변화에 따른 특성을 빠른 시간 내에 파악할 수 있는 등가자기회로법(equivalent magnetic circuit method)을 활용하여 콜레노이드(colenoid) 타입의 선형 액츄에이터 설계 알고리즘을 제시하였다. 우선 선형 액츄에이터의 중요치수가 결정되면 등가자기회로법에 의해 슬롯 폭 비율 및 인가전류에 따른 클램핑력으로 파라미터 맵(parameter map)을 완성하고 이를 활용하여 효율적인 슬롯 폭 비율을 결정하였다. 또한 최대 클램핑력(clamping force)을 얻기 위해 극 폭 조절 알고리즘을 수행하여 최적의 극 폭 치수를 선정하였으며 이를 바탕으로 인가전류에 따른 클램핑력을 계산하여 40 kN 이상 출력하기 위한 최적의 극 수, 극 폭 치수 및 인가전류를 결정하였다. 제안된 설계 알고리즘은 최적설계 방법인 반응표면법(response surface method)과 비교하여 제안한 설계 알고리즘의 타당성을 검증하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.520-522
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• 2008

A novel two-switch active clamp forward converter suitable for high input voltage applications is proposed. The main advantage of the proposed converter, compared to the conventional active forward converters, is that circuit complexity is reduced and the voltage stress of the main switches is effectively clamped to either the input voltage or the clamping capacitor voltage by two clamping diodes without limiting the maximum duty ratio. Also, the clamping circuit does not include additional active switches, so a low cost can be achieved without degrading the efficiency. Therefore, the proposed converter can feature high efficiency and low cost for high input voltage applications. The operational principles, features, and design considerations of the proposed converter are presented in this paper. The validity of this study is confirmed by the experimental results from a prototype with 200W, 375V input, and 12V output.

• Journal of Power Electronics
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• 제11권4호
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• pp.499-506
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• 2011

This paper presents an interleaved active-clamping zero-voltage-switching (ZVS) forward-flyback converter without an output choke. The presented topology has two active-clamping circuits with two separated transformers. Because of the interleaved operation of the converter, the output current ripple will be reduced. The proposed converter can approximately share the total load current between the two secondaries. Therefore, the transformer copper loss and the rectifier diodes conduction loss can be decreased. The output capacitor is made of two series capacitors which reduces the peak reverse voltage of the rectifier diodes. The circuit has no output inductor and few semiconductor elements, such that the adopted circuit has a simpler structure, a lower cost and is suitable for high power density applications. A detailed analysis and the design of this new converter are described. A prototype converter has been implemented and experimental results have been recorded with an ac input voltage of 85-135Vrms, an output voltage of 12V and an output current of 16A.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 B
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• pp.1117-1119
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• 2002

In this paper, we have developed a ZVS half-bridge converter with a clamping circuit for the DC power source of PDP circuit. The clamping circuit in the developed converter reduces the oscillating current of the switch by resonant inductor and parasitic parameters in output rectifier diodes. Finally, comparing the experimental results of the developed converter to the conventional ZVS half-bridge converter, it is clarified that the developed converter is more efficient and lower noise than the conventional one.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 춘계학술대회 논문집 에너지변화시스템부문
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• pp.156-160
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• 2009

This paper presents the interleaved active-clamping ZVS(Zero Voltage Switching) forward converter, which is mainly composed of two active-clamping forward converters. Only two switches are required, and each one is the auxiliary switch for the other. The circuit complexity and cost are thus reduced. The leakage inductance of the transformer or an additional resonant inductance is employed to achieve ZVS during the dead times. The duty cycles are not limited to be equal and within 50%. The complementary switching and the resulted interleaved output inductor currents diminish the current ripple in output capacitors. Accordingly, the smaller output chokes and capacitors lower the converter volume and increase the power density. Detailed analysis and design of this new interleaved active-clamping forward converter are described.

• 한국통신학회논문지
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• 제29권4A호
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• pp.363-369
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• 2004

본 논문에서는 파장분할다증(WDM) 첨가(add)/절취(drop)망에서 채널의 add/drop에 따라 망 내에 있는 EDFA의 이득을 제어함에 있어 세계 최초로 외란 간측기법을 적용하는 새로운 이득-클램핑(gain-clamping) 방법을 제안한다. 이득-클램핑을 위한 제어신호는 공칭 제어신호와 채널의 add/drop에 따른 이득변동을 보정하기 위한 부가제어신호로 구성된다. 외란 관측기법에 근거하여, 부가 제어신호는 채별의 add/op에 의해 발생하는 추정 외란을 보정할 수 있도록 설계하였다. 이러한 부가 제어신호를 생성하는 회로는 간단한 전자소자를 이용하여 쉽게 구현할 수 있다. 모의실험을 통해 본 논문에서 제안하는 방법을 사용할 때 채널의 add/drop 과정에서 EDFA의 출력 파형에 나타나는 이득변화에 따른 요철이 최소로 됨을 보여줌으로써 본 방법이 기존의 여타 방법들에 비해 월등함을 입증하였다.

• 전력전자학회논문지
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• 제10권2호
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• pp.194-202
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• 2005

본 연구는 새로운 AC PDP(Plasma Display Panel)용 멀티레벨 에너지 회수회로에 관한 연구로서, 기존 멀티레벨 구동회로의 장점을 그대로 유지하면서 문제점을 해결한 새로운 멀티레벨 구동회로를 제안한다. 기존의 멀티레벨 구동회로는 Weber회로의 하드스위칭 문제를 개선하였지만 공진 인덕터에 기생공진전류가 존재하고 Vs/2유지구간이 존재한다. 제안한 회로는 기존 회로에 비해 인덕터의 수를 반으로 줄여 회로를 간단히 하고 공진 인덕터의 기생 공진전류와 Vs/2유지구간을 제거하였으며 CIM(Current Injection Method)을 사용하여 하드스위칭 문제를 해결하였다. 또한 풀브리지 구동회로에 직렬 연결된 스위칭 소자에 NPC(Neutral Point Clamping)기법을 적용하여 각 스위칭 소자에 전압이 균등하게 분배되도록 하였다. 그리고 제안회로의 동작을 모드별로 해석하였으며, PSpice 프로그램으로 시뮬레이션하고 회로를 구성하여 실험함으로써 제안한 회로의 유용성을 입증하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.124-126
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• 1988

The induction motor is constantly operated by general source, thus its speed control is employed an inverter system which can convert DC into AC. The CSI(Current Source Inverter) which have a commutation capacitor in its circuit is liable to cause a voltage spike that it is due to charge and discharge of commutation capacitor. And six phases inverter makes a number of harmonics. These have a effect upon the induction motor badly. This paper aims to suggest a way to reduce such adverse effects by maximally cutting the voltage spike as well as by eliminating a number of harmonics through the operation of Multi-HFCSI.

• 대한전기학회논문지
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• 제38권4호
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• pp.269-278
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• 1989

When the induction motor is operated by CSI, the commutation capacitance in the CSI circuit is increased according to the increase of large capacitor system. The output voltage spikes are generated at the moment of charge and discharge of the commutation capacitor. Also, since output current comprise a great number of harmonics, torque ripples of the motor are generated, having bad effects on the motor. In this study, by adopting the 18-phase multiple high Frequency Current Source Inverter (HFCSI), torque ripples generated by the voltage spikes are mostly eliminated except the 17th and 19th harmonics. To reduce the voltage spikes comprised in the output voltage, particularly, the methods of eliminating the cause of bad effect upon the motor are proposed in this paper. In the proposed method, by using additional voltage Clamping Curcuit (VCC), it is possible to select the values of commutation capacitor energy loss in commutating, the commutating capacitor, and the capacitor in the clamping circuit.