• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.7
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• pp.666-676
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• 1992

In this paper, algorithm and testable circuit to find all PSF(Pattern Sensitive Fault ) occured in RAM were proposed. Conventional test circuit and algorithm took much time in testing because consecutive test for RAM cells or f-dimensional memory struciure was not employed. In this paper, methodology for parallel RAM-testing was proposed by compensating additional circuit for test to conventional RAM circuit. Additional circuits are parallel comparator, error detector, group selector circuit and a modified decoder used for parallel testing. And also, the constructive method of Eulerian path to obtain efficient test pattern was performed. Consequently, If algorithm proposed in this paper Is used, the same operations as 32sxwor4 lines will be needed to test b x w=n matrix RAM. Circuit simulation was performerd, and 10 bits x :If words testable RAM was designed.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.3
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• pp.535-540
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• 1987

This paper proposes a circuit partitioning method and a multifunctional BILBO which can perform the multimodule test in the case of testing VLSI circuits. By using these circuit partitioning method and multifunctional BILBO, test time and cost can be reduced greatly by performing the pipeline test method. And the quantity of circuit that shold be added for testing is also reduced in half by interposing only one BILBO between each module. Also, we confirmed that the multifunctional BILBO proposed here has high error detection capability by analyzing error detection capability of this multifunctional BILBO in mathematics.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10b
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• pp.569-572
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• 1992

This paper describes a new method of pseudorandom testing of a digital circuit by use of correlation method and a neural network. The authors have recently proposed a new method of fault diagnosis of logical circuit by applying a pseudorandom M-sequence to the circuit under test, calculating the crosscorrelation function between the input and the output, and comparing the crosscorrelation functions with the references. This method, called MSEC method, is further extended by using a neural network in order to not only detect the existence of faults but also find the place or location of the faults. An experiment by using a simple digital circuit shows enough applicability of this method to industrial testing of circuit board.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.53-60
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• 1997

In this paper, an efficient BILBO(named EBILBO) is proposed for batch testing application when a BIST (built-in self test) circuit is implemented on ASIC. In a large and complex circuit, the proposed algorithm of batch testing has one pin-count that can easily control 4 test modes in the normal speed of circuit operation. For the implementation of the BIST cifcuit, the test patern needed is generated by PRTPG(pseudo-random test pattern generator) and the ouput is observed by proposed algorithm is easily modified, such as the modelling of test pattern genration, signature EBILBO area and performance of the implemented BIST are evaluated using ISCAS89 benchmark circuits. As a resutl, in a circuit above 600 gates, it is confirmed that test patterns are genrated flexibly about 500K as EBILBO area is 59%, and the range of fault coverage is from 88.3% to 100%. And the optimized operation frequency of EBILBO designed and the area are 50MHz and 150K respectively. On the BIST circit of the proposed batch testing, the test mode of EBILBO is able to execute as realtime that has te number of s$\^$+/n$\^$+/(2s/2p-1) clocks simultaneously with the normal mode of circuit operation. Also the proposed algorithm is made of the library with VHDL coding thus, it will be widely applied to DFT (design for testability) that satisfies the design and test field.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.7
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• pp.105-113
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• 2011

The study about three-phase synthetic making test using DC power has been performed in order to increase the making test capacity on Vacuum Circuit Breaker. And, it made possible to solve the limitations that short-circuit testing facilities can not fulfill the testing requirements of VCB exceeding three-phase 36[kV] 31.5[kA]. By using DC power and high speed spark-gap switch, this method made the equivalence with the pre-arc that occurred during the making process under the fault condition of power system. As results, KERI(Korea Electrotechnology Research Institute) could have capacity to carry out type test for VCB under three-phase 52[kV] 40[kV], which satisfies the IEC Standard.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.3
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• pp.517-526
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• 1987

This paper proposes a new testable design for Zipper CMOS circuits. This design provides an additional feedback loop (called self oscillation loop) whichin the circuit, for testability. The circuit is tested only by observing the oscillation on the loop. The design can be applied to the multistage as well as the single stage, and can detect multiple faults which are undetectable by the conventional testing method. The application and evaluation of test patterns become easy and fault-free responses are not necessary. If the conventional testing method is applied to the sequential Zipper CMOS circuit with the LSSD design technique, it has the serious defect that the initial value may change due to intermediate test patterns and much time taken to apply the necessary test patterns. By using the proposed design, however, the sequential Zipper CMOS circuit with the LSSD design technique can be easily tested without such a defect. Also, the validity of the design is verified by performing the circuit level simulation.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.11
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• pp.1434-1444
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• 1995

Current test has recently been known to be a promising testing method in CMOS VLSI because conventional voltage test can not make sure of the complete detection of bridging, gate-oxide shorts, stuck-open faults and etc. This paper presents a new BIC(built-in current sensor) for the internal current test in CMOS logic circuit. A single phase clock is used in the BIC to reduce the control circuitry of it and to perform a self- testing for a faulty current. The BIC is designed to detect the faulty current at the end of the clock period, so that it can test the CUT(circuit under test) with much longer critical propagation delay time and larger area than conventional BICs. The circuit is composed of 18 devices and verified by using the SPICE simulator.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.8-21
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• 1997

In this paper, we consider resistive shorts on gate-source, gate-drain, and drain-source as well as opens in MOS FETs included in typical memory cell of VLSI SRAM and analyze behavior of memory by using PSPICE simulation. Using conventional fault models and this behavioral analysis, we propose linear testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ (quiescent power supply current) testing simultaneously to improve functionality and reliability of memory. Finally, we implement BIST (built-in self tsst) circuit and BICS(built-in current sensor), which are embedded on memory chip, to carry out functional testing efficiently and to detect various defects at high-speed respectively.

• Proceedings of the KIEE Conference
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• 2001.07a
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• pp.38-40
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• 2001

Measuring technology based on the computer and software is used worldwideiy by the aids of remarkably improved digital technology and measuring devices, and the electro- magnetic interference due to high currents and high voltages is being solved by the helps of applied optic instrumentation technology. The automatic acquisition, analysis and storage system of test data is available for utilizing the numerical computation technology. The measuring accuracy and testing efficiency are thus much higher because of the developed technologies. In this paper, the construction of data acquisition system in KERI including measuring devices and its application to the short circuit test are described, and additionally the algorithm of the analyzing program for the automatic process of test data and the results of analyses are described.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.3
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• pp.401-417
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• 1994

In this paper, a new testable design technique for domino CMOS circuits is proposed to detect stuck-at(s-at), stuck-open(s-op) and stuck-on(s-on) faults in the circuits by observing logic test reponses. The proposed technique adds one pMOS transistor per domino CMOS gate for s-op and s-on faults testing of nMOS transistors and one nMOS transistors and one nMOS transistor per domino gate or multilevel circuit to detect s-on faults in pMOS transistors of inverters in the circuit. The extra transistors enable the proposed testable circuit to operate like a pseudo static nMOS circuit while testing nMOS transistors in domino CMOS circuits. Therefore, the two=phase operation of a precharge phase and a evaluation phase is not needed to keep the domino CMOS circuit from malfunctionong due to circuit delays in the test mode, which reduces the testing time and the complexity of test generation. Most faults of th transistors in the proposed testable domino CMOS circuit can be detected by single test patterns. The use of single test patterns makes the testing of the proposed testable domino CMOS circuit free from path delays, timing skews, chage sharing and glitches. In the proposed design, the testing of the faults which, require test sequences also becomes free from test invalidation. The conventional automatic test pattern generators(ATPG) can be used for generating test patterns to detect faults in the circuits.