• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.2
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• pp.347-353
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• 2018

In this paper, we studied a design method for a band-pass waveguide filter with a modified H-type resonant iris (RI) placed in a thin transverse wall of a rectangular waveguide. The horizontal straight gap at the center of a conventional H-shaped iris is modified to a U-shaped one to increase the equivalent capacitance, and the equivalent inductance is improved by changing the vertical two straight slots into C-shaped ones. From some simulation results for the frequency response of the proposed RI, it was observed that the proposed iris was advantageous for reducing its size and having better cutoff, compared to typical H-shaped one. Equivalent inductance, capacitance, and quality factor of the proposed RI were extracted to analyze its performance. A third-order band pass filter using the proposed modified H-shaped iris was designed and, it was observed that the filter operated in the frequency range of 9.18-9.84 GHz with its insertion loss of 0.3 dB and return loss of 14 dB.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.9
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• pp.4165-4170
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• 2012

In this paper, a method for the improvement in the gain and bandwidth of a microstrip-fed broadband planar quasi-Yagi antenna (QYA) is studied. The broadband characteristics of the QYA are achieved from the coplanar strip-fed planar dipole driver and a parasitic director close to the driver. In order to obtain stable gain variation over the required frequency band, a director and a ground reflector are appended to the driver having a nearby parasitic director. The QYA is fed through an integrated balun composed of a microstrip line and a slot line which are terminated in a short circuit. By adjusting the feeding point, a broadband impedance matching is obtained. A QYA with an operating frequency band of 1.75-2.7 GHz and a gain > 4.5 dBi is designed and fabricated on an FR4 substrate with dielectric constant of 4.4 and thickness of 1.6mm. The experimental results show that the fabricated antenna has good performance such as a broad bandwidth of 59.7%(1.55-2.87 GHz), a stable gain between 4.7-6.5 dBi, and a front-to-back ratio > 10 dB. The measured data agree well with the simulation, which validates this study.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.2
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• pp.16-23
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• 2006

This paper presents a novel single-stage high frequency resonant inverter link type DC-DC converter using zero voltage switching with high power-factor. The proposed topology is integrated half-bridge boost rectifier as power factor corrector(PFC) and half-bridge high frequency resonant converter into a single-stage. The input stage of the half-bridge boost rectifier works in discontinuous conduction mode(DCM) with constant duty cycle and variable switching frequency. So that a boost converter makes the line current follow naturally the sinusoidal line voltage waveform. Simulation results have demonstrated the feasibility of the proposed high frequency resonant converter. Characteristics values based on characteristics analysis through circuit analysis is given as basis data in design procedure. Also, experimental results are presented to verify theoretical discussion. This proposed inverter will be able to be practically used as a power supply in various fields as induction heating applications, fluorescent lamp and DC-DC converter etc.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.6
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• pp.2747-2753
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• 2011

In this paper, a PWM current-mode DC-DC boost converter for mobile phone flash application has been proposed. The converter which is operated with 5 Mhz high switching frequency is capable of reducing mounting area of passive devices such as inductor and capacitor, consequently is suitable for compact mobile phones. This boost converter consists of a power stage and a control block. Circuit elements of the power stage are inductor, output capacitor, MOS transistors and feedback resistors. Meanwhile, the control block consists of pulse width modulator, error amplifier, oscillator etc. Proposed boost converter has been designed and verified in a $0.5\;{\mu}m$ 1-poly 2-metal CMOS process technology. Simulation results show that the output voltage is 4.26 V in 3.7 V input voltage, output current 100 mA which is larger than 25 ~ 50 mA in conventional 500 Khz driven converter when the duty ratio is 0.15.

• The Transactions of the Korea Information Processing Society
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• v.5 no.6
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• pp.1610-1619
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• 1998

The ABR service class provides feedback based traffic control to transport bursty data traffic efficiently. Feedback based congestion control has first been studied to be applied to unicast connections. Recently. several congestion control algorithms for multicast connections have also been proposed as the number of ABR applications requiring multicast increases. With feedback based congestion control, the effectiveness of a traffic control scheme diminishes as propagation delay increases. Especially for a multicast connection, a remote destination may suffer unfair service compared to a local destination due to the delayed feedback. Amelioration of the disadvantages caused by feedback delay is therefore more important for remote destinations in multicast connections. This paper proposes a new switch behavior to provide effective feedback based mathc control for rentoh destinations. The proposed switches adjust the service rate dynamically in accordance woth the state of the downstream, that is, the congestion of the destinaion is immediately controlled by the nearest apstream switch before the source to ramp down the transmission rate of the connection. The proposed switch has an implementation overhead to have a separate buffer for each VC to adjust the service rate in accordance with a backward Rm cell of each VC. The buffer requirement id also increased at intermediate switches. Simulation results show that the proposed switch reduces the cell loss rate in both the local and the remote destinations and slso amelioratd the between the two destinations.

• Korean Journal of Remote Sensing
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• v.30 no.2
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• pp.293-302
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• 2014

Radar systems are used in remote sensing mainly as space-borne, airborne and ground-based Synthetic Aperture Radar (SAR), scatterometer and Doppler radar. Those systems are composed of expensive equipments and require expertise and professional skills for operation. Because of the limitation in getting experiences of the radar and SAR systems and its operations in ordinary universities and institutions, it is difficult to learn and exercise essential principles of radar hardware which are essential to understand and develop new application fields. To overcome those difficulties, in this paper, we present the construction and experiment of a low-cost educational radar system based on the blueprints of the MIT Cantenna system. The radar system was operated in three modes. Firstly, the velocity of moving cars was measured in Doppler radar mode. Secondly, the range of two moving targets were measured in radar mode with range resolution. Lastly, 2D images were constructed in GB-SAR mode to enhance the azimuth resolution. Additionally, we simulated the SAR raw data to compare Deramp-FFT and ${\omega}-k$ algorithms and to analyze the effect of antenna positional error for SAR focusing. We expect the system can be further developed into a light-weight SAR system onboard a unmanned aerial vehicle by improving the system with higher sampling frequency, I/Q acquisition, and more stable circuit design.

• Journal of the Korean Society of Marine Environment & Safety
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• v.25 no.6
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• pp.802-808
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• 2019

DC motors are used extensively on shipboard, including as the ship's winch operating motor, owing to their simple speed control and excellent output torque characteristics. Moreover, they were used as propulsion motors in the early days of electric propulsion ships. However, mechanical rectifiers, such as brushes, used in DC motors have certain disadvantages. Hence, brushless DC (BLDC) motors are increasingly being used instead. While the electrical characteristics of both types of motors are similar, BLDC motors employ electronic rectifying devices, which use semiconductor elements, instead of mechanical rectifying devices. The inverter system for driving conventional BLDC motors uses a two-phase excitation method so that the waveform of the back electromotive force becomes trapezoidal. This causes harmonics and torque ripple in the phase current switching period in which the winding wire through which the current flows is changed. Researchers have studied and presented various methods to reduce the harmonics and torque ripple. This study applies a cascaded H-bridge multilevel inverter, which implements a proportional-integral speed current controller algorithm in the driving circuit of the BLDC motor for electric propulsion ships using a power analysis program. The simulation results of the modeled BLDC motor show that the driving method of the proposed BLDC motor improves the voltage waveform of the input side of the motor and remarkably reduces the harmonics and torque ripple compared with the conventional driving method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.673-684
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• 2003

A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome this problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. Using the proposed gain control scheme, a low-voltage and high-speed CMOS VGA is designed. HSPICE simulation results using a 0.25${\mu}{\textrm}{m}$ CMOS process parameters show that the designed VGA provides a 3dB bandwidth of 360MHz and a 80dB gain control range in 2dB step. Gain errors are less than 0.4dB at 200MHz and less than l.4dB at 300MHz. The designed circuit consumes 10.8mA from a 2.5V supply and its die area is 1190${\mu}{\textrm}{m}$${\times}$360${\mu}{\textrm}{m}$.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.80-87
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• 2013

A novel instrumentation amplifier(IA) using positive polarity current-conveyor(CCII+) for electronic measurement systems with low cost, wideband, and gain control with wide range is designed. The IA consists of two CCII+, three resistor, and an operational amplifier(op-amp). The principal of the operating is that the difference of two input voltages applied into two CCII+ used voltage and current follower converts into same currents, and then these current drive resistor of (+) terminal and feedback resistor of op-amp to obtain output voltage. To verify operating principal of the IA, we designed the CCII+ and used commercial op-amp LF356. Simulation results show that voltage follower used CCII+ has offset voltage of 0.21mV at linear range of ${\pm}$4V. The IA had wide gain range from -20dB to 60dB by variation of only one resistor and -3dB frequency for the gain of 60dB was 400kHz. The IA also has merits without matching of external resistor and controllable offset voltage using the other resistor. The power dissipation of the IA is 130mW at supply voltage of ${\pm}$5V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.26-31
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• 2009

A new LFSR based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, smax, virtually. The performance of a conventional LFSR reseeding scheme highly depends on smax. In this paper, by using different clock frequencies between an LFSR and scan chains, and grouping the scan cells, we could reduce smax virtually. H the clock frequency which is slower than the clock frequency for the scan chain by n times is used for LFSR, successive n scan cells are filled with the same data; such that the number of specified bits can be reduced with an efficient grouping of scan cells. Since the efficiency of the proposed scheme depends on the grouping mechanism, a new graph-based scan cell grouping heuristic has been proposed. The simulation results on the largest ISCAS 89 benchmark circuit show that the proposed scheme requires less memory storage with significantly smaller area overhead compared to the previous test compression schemes.