• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.343-345
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• 1996

In the case of synchronous machines, certain power system disturbances cause current to assume negative values when no static converter is present. But the converter prevents negative current from flowing, so that overvoltages occur. The overvoltages can be effectively limited as crowbar circuit using GTO. The crowbar circuit with current limiting resistor absorbs energy when overvoltage comes from power system repeatedly. The newly proposed circuit is verified through simulation and experiment

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.319-329
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• 2016

High-level design aids are mandatory for design of a continuous-time delta-sigma modulator (CTDSM). This paper proposes a top-down methodology design to generate a noise transfer function (NTF) which is compensated for excess loop delay (ELD). This method is applicable to low pass loop-filter topologies. Non-ideal effects including ELD, integrator scaling issue, finite op-amp performance, clock jitter and DAC inaccuracies are explicitly represented in a behavioral simulation of a CTDSM. Mathematical modeling using MATLAB is supplemented with circuit-level simulation using Verilog-A blocks. Behavioral simulation and circuit-level simulation using Verilog-A blocks are used to validate our approach.

• Progress in Superconductivity and Cryogenics
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• v.23 no.3
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• pp.51-54
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• 2021

The DC system has less power loss compared to the AC system because there is no influence of frequency and dielectric loss. However, the zero-crossing point of the current is not detected in the event of a short circuit fault, and it is difficult to interruption due to the large fault current that occurs during the opening, so the reliability of the DC breaker is required. As a solution to this, an LC resonance DC circuit breaker combined a superconducting element has been proposed. This is a method of limiting the fault current, which rises rapidly in case of a short circuit fault, with the quench resistance of the superconducting element, and interruption the fault current passing through the zero-crossing point through LC resonance. The superconducting current limiting element combined to the DC circuit breaker plays an important role in reducing the electrical burden of the circuit breaker. However, at the beginning of a short circuit fault, superconducting devices also have a large electrical burden due to large fault currents, which can destroy the element. In this paper, the reactor is connected to the source side of the circuit using PSCAD/EMTDC. After that, the change of the fault current according to the reactor capacity and the electrical burden of the superconducting element were confirmed through simulation. As a result, it was confirmed that the interruption time was delayed as the capacity of the reactor connected to the source side increased, but peak of the fault current decreased, the zero-crossing point generation time was shortened, and the electrical burden of the superconducting element decreased.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.960-964
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• 2003

In this paper, the CMOS integrated circuit technique for implementing current-mode maximum and minimum operations scheme is described. The maximum and minimum operations are incorporated into the same scheme with parallel processing. Using this scheme as the basic unit, an analog three-input maximum, median, and minimum circuit is designed. The performance of the proposed circuit shows a very sharp transfer characteristic and high accuracy. The proposed circuit achieves a high-speed operation, which is suitable for real-time systems. The PSPICE simulation results demonstrating the characteristic of the proposed circuit are included.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.9
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• pp.1566-1570
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• 2007

[ $SF_6$ ] gas circuit breakers are widely used for short circuit current interruption in EHV(Extra High Voltage) or UHV(Ultra High Voltage) power systems. To develop $SF_6$ gas circuit breakers, the arc resistance value is necessary to compare experimental results to numerical ones. The arc resistance value can be obtained from a breaking test with a $SF_6$ gas circuit breaker. The direct testing or synthetic testing facility is widely used to verify the breaking ability for $SF_6$ gas circuit breakers. We employed the simplified synthetic testing facility to test a $SF_6$ gas circuit breaker prototype. The arc resistance characteristic was measured and calculated under the various experimental conditions. This arc resistance value can be used for verifying the numerical results from arc simulation in a circuit breakers.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.179-182
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• 2003

A simulation on bootstrapping circuit has been performed by modelling a coaxial cable as a transmission line. It is shown that the bootstrapping circuit could be unstable due to the transmission line effect though an ideal amplifier is used. While the conventional bootstrapping circuit does not cancel the input capacitance of the input buffer, a new bootstrapping circuit that cancels input capacitance of the input buffer has been proposed. The proposed bootstrapping circuit consists of the input buffer of which gam is larger than 1 and a feedback resistor to control the loop gain. The proposed bootstrapping circuit has higher input impedance than that of the conventional circuit.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.2
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• pp.244-250
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• 1994

This paper presents the design of a new turn-off gate drive circuit for GTO which can accomplish faster turn-off switching. The major disadvantage of the conventional turn-off gate drive technique is that it has a difficulty in realizing high negative diS1GQT/dt because of VS1RGM(maximum reverse gate voltage) and stray inductances of turn-off gate drive circuit[1~2]. The new trun-off gate drive technique can overcome this problem by adding another turn-off gate drive circuit to the conventional turn-off gate drive circuit. Simulation and experimental results of the new turn-off gate drive circuit in conjunction with chopper circuit verify a faster turn-off switching performance.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.1
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• pp.101-107
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• 1988

This paper proposes a circuit extractor which extracts a netlist from the CIF input file cntaining the layout mask artwork informations. The circuit extractor extracts transistors and their interconnections, and calculates circuit parameter such as parasitic resistance and parasitic capacitance from the mask informations. When calculating the parasitic resistance, we consider the current flow path to reduce the errors caused by the resistance approximation. Similarly, we consider the coupling capacitance which has an effect on the circuit characteristics, when the parasitic capacitances are calculated. Therefore, using these parameter values as an input to circuit simulation, the circuit characteristics such as delay time can be estimated accurately. The presented circuit extraction algorithm uses a multiple storage quad tree as a data sturucture for storing and searching the 2-dimensional geometric data of mask artwork. Also, the proposed algorithm is technologically independent to work across a wide range of MOS technologies without any change in the algorihm.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.513-513
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• 2000

An integrable circuit technique for implementing high-speed analog two-input Max/Min circuit is described. The realization method is suitable for fabrication using CMOS technology. The proposed circuit comprises a current mirror and electronic switch connected with a absolute value circuit. The maximum or minimum operation of the proposed circuit can be selected by an external control voltage. The proposed analog Max/Min circuit has a very sharp transfer characteristic and is suitable for real-time systems. Simulation results verified the circuit performances are agreed with the expected values.

• Proceedings of the KIEE Conference
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• 2006.07a
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• pp.115-116
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• 2006

Since the discovery of the high-temperature superconductors, many researches have been performed for the practical applications of superconductivity technologies in various fields. As results, significant progress has been achieved. Especially, Superconducting Fault Current Limiter (SFCL) offers an attractive means to limit fault current in power systems. The SFCLS, in contrast to current limiting reactors or high impedance transformers, are capable of limiting short circuit currents without adding considerable voltage drop and energy loss to power systems during normal operation. Under fault conditions, a resistance is automatically inserted into the power grid to limit the peak short-circuit current by transition from the superconducting state to the normal state, the quench. The advantages, like fail safe operation and quick recovery, make SFCL very attractive, especially for rapidly growing power systems with higher short-circuit capacities. In order to verify the effectiveness of the SFCL, in this paper, the analysis of fault current and voltage stability assessment in a sample distribution system and a transmission system are performed by the PSCAD/EMTDC based simulation method. Through the simulation, the advantage of SFCL application is shown, and the effective parameters of the SFCL are also recommended for both distribution and transmission systems. A resistive type component of SFCL is adopted in the analysis. The simulation results demonstrate not only the effectiveness of the proposed simulation scheme but also SFCL parameter assessment technique.