• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.370-374
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• 1991

This paper presents a static circuit model for static ant dynamic simulation of induction motors and identification of motor parameters. Instead of usual T-circuits, equivalent ${\pi}$-circuit has been proposed so that power Inputs into motor terminals can very easily calculated with very well known load flow method. It has been shown that, with wide range variation of applied voltage and frequency, successful static simulations can be performed and further the proposed static model can be used to simulate dynamic characteristics. Finally it is shown also that motor parameters can easily be identified based on the proposed static circuit.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.1
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• pp.93-102
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• 1994

This paper, presents SECRET(SEC REliability Tool), which predicts reliability problems related to the hot-carrier and electromigration effects on the submicron MOSFETs and interconnections. To simulate DC and AC lifetime for hot-carrier damaged devices, we have developed an accurate substrate current model with the geometric sensitivity, which has been verified over the wide ranges of transistor geometries. A guideline can be provided to design hot-carrier resistant circuits by the analysis of HOREL(HOT-carrier RFsistant Logic) effect, and circuit degradation with respect to physical parameter degradation such as the threshold voltage and the mobility can also be expected. In SECRET, DC and AC MTTF values of metal lines are calculated based on lossy transmission line analysis, and parasitic resistances, inductances and capacitances of metal lines are accurately considered when they operate in the condition of high speed. Also, circuit-level reliability simulation can be applied to the determination of metal line width and-that of optimal capacitor size in substrate bias generation circuit. Experimental results obtained from the several real circuits show that SECERT is very useful to estimate and analyze reliability problems.

• Journal of Power Electronics
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• v.13 no.4
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• pp.729-736
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• 2013

Knowledge of a power semiconductor's operating temperature is important in circuit design and converter control. Designing appropriate circuitry that does not affect regular circuit operation during virtual junction temperature measurement at actual operating conditions is a demanding task for engineers. The proposed method enables virtual junction temperature estimation with a dedicated modified gate driver circuit based on real-time measurement of a semiconductor's quasi-threshold voltage. A simulation was conducted before the circuit was designed to verify the concept and to determine the basic properties and potential drawbacks of the proposed method.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.510-510
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• 2000

This paper introduces the design of BiCMOS latched comparator circuit for high-speed system application, which can be used in data conversion, instrumentation, communication system etc. By exploiting the advantage technology of the combination of both the bipolar transistor and the CMOS transistor devices. The comparator circuit includes an input stage that combines MOS sampling with a bipolar regenerative amplifier. The resistive load of conventional current-steering comparator is replaced by a load, which is made by a NMOS transistor. The advantage of design and PSPICE simulation of BiCMOS latched comparator are the circuit will obtain wide bandwidth with lowest power consumption at a single supply voltage. All the characteristics of the proposed BiCMOS latched comparator circuit is carried out by simulation program.

• Progress in Superconductivity
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• v.4 no.1
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• pp.37-41
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• 2002

In this work. we have designed two different kinds of Rapid Single Flux Quantum (RSFQ) OR-gates. One was based on the already developed RSFQ cells and the other was aimed to develop a more compact version. In the first circuit, we used a combination of two D Flip-Flops and a merger and in the other circuit we used a combination of RS Flip-Flops and Confluence Buffer. We tested the circuit performance by using the simulation tools, Xic and Wrspice. We obtained the operation margins of the circuit elements by a margin calculation program, and we obtained the minimum operation margins of $\pm$30%. The circuits were laid out, aimed to fabricate by using the existing KRISS Nb process. KRISS Nb process includes the $Nb／Al_2$$O_3$／Nb trilayer fabricated by DC magnetron sputtering and the reactive ion etching technique for the definition of the features. The major tools used in the layouts were Xic and L-meter.

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.237-239
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• 1994

The MOS-controlled thyristor(MCT) is a new power semi-conductor device that combines four layers thyristor structure presenting regenerative action and MOS-gate providing controlled turn-on and turn-off. The MCT has very fast switching speed owing to voltage controlled MOS-gate, and very low on-state voltage drop resulting from regenerative action of four layers thyristor structure. In addition, because of a higher dv/dt rating and di/dt rating, gate drive circuit and snubber circuit can be simpler comparing to other power switching devices. So recently much interest and endeavor is being applied to develop the performance and ratings of the MCT. This paper describes the switching characteristic of the MCT for its practical applications and presents a model for PSPICE circuit simulation. The model for PSPICE circuit simulation is compared to the experimental result using MCTV75P60F1 made by Harris co..

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.1
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• pp.13-17
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• 2013

In this paper, we designed a charge pump circuit using level shifter for LED driver IC. The designed circuit makes the 15 V output voltage from the 5 V input in condition of 50 kHz switching frequency. The prototype chip which include the proposed charge pump circuit and its several internal sub-blocks such as oscillator, level shifter was fabricated using a 0.35 um 20 V BCD process technology. The size of the fabricated prototype chip is 2,350 um ${\times}$ 2,350 um. We examined performances of the fabricated chip and compared its measured results with SPICE simulation data.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.318-327
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• 2010

This paper deals with analysis on dynamic characteristic and circuit parameter of linear switched reluctance motor by electromagnetic analytical method. Above all, using space harmonic method, which is electromagnetic method, the air-gap flux density is analyzed in the both align and unaign positions, and the inductance profile, force characteristic and resistance per phase are calculated by means of the process. The validity of the analyzed results are demonstrated by the finite element method(FEM) and manufacture of the prototype machine. Second, the dynamic simulation is analyzed by the use of circuit parameters derived from analytical method, and the operating system of the prototype machine is manufactured to demonstrated the validity of simulation analysis. As a result, it is considered that the characteristic equation suggested in this paper will contribute to the design, analysis and application of LSRM.

• Journal of Electrical Engineering and Technology
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• v.5 no.2
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• pp.264-269
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• 2010

This paper presents the analysis of the dielectric characteristics of a hot $SF_6$ gas in a gas circuit breaker. Hot gas flow is analyzed using the FVFLIC method considering the moving boundary, material properties of real $SF_6$ gas, and arc plasma. In the arc model, the re-absorption of the emitted radiation is approximated with the boundary source layer where the re-absorbed radiation energy is input as an energy source term in the energy conservation equation. The breakdown criterion of a hot gas is predicted using the critical electric field as a function of temperature and pressure. To validate the simulation method, breakdown voltage for a 145kV 40kA circuit breaker was measured for various conditions. Consistent results between the simulation and experiment were confirmed.

• Proceedings of the KIEE Conference
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• 2003.07c
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• pp.1418-1420
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• 2003

In this study capacitance and dielectric loss tan${\delta}$were measured with frequency changes for commercial $Z_nO$ varistors with pin-type leads and equivalent circuit simulation was proposed. The leakage inductance in pin leads and the stray caoacitance could be seperated from the dielectric characteristics of $Z_nO$ varistors by the simulation of equivalent circuit. The equivalent circuit model considered semiconduction layer, dielectric layer and depletion layer as the grain boundary structure of varistor is well fitted to the observed data.