• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.2000-2003
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• 2002

In this paper, an IC chip of a cell- network type circuit constructed with 1-dimensional chaos circuits is reported. The circuit, is designed by sing switched-current (Sl) techniques. In the proposed circuit, by controlling connections of cells, an S- dimensional circuit (S ＝ 1, 2, 3,…) and a synchronization system can be constructed easily. Furthermore, in spite of faults of a few cells, the circuit can reconstruct above-mentioned systems only to change connections of cells. This feature will open up new vista for engineering applications which are used in a distance place such as space, deep sea, etc. since it is difficult to repair faults of these application systems. To investigate the characteristics of the circuit, SPICE simulations are performed. The VLSI chip is fabricated from the layout design using a CAD tool, MAGIC. The proposed circuit is integrable by a standard 1.2 $\mu\textrm{m}$ CMOS technology.

• The Journal of the Acoustical Society of Korea
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• v.20 no.1E
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• pp.14-19
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• 2001

We have proposed BIST method and circuit for embedded 16M SDRAM with logic. It can test the AC parameter of embedded 16M SDRAM using the BIST circuit capable of detecting the address of a fail cell installed in an Merged Memory with Logic(MML). It generates the information of repair for redundancy circuit. The function and AC parameter of the embedded memory can also be tested using the proposed BIST method. It is possible to test the embedded SDRAM without external test pin. The total gate of the BIST circuit is approximately 4,500 in the case of synthesizing by 0.25μm cell library and is verified by Verilog simulation. The test time of each one AC parameter is about 200ms using 2Y-March 14n algorithm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.4
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• pp.216-231
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• 2001

Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.

• Journal of the Semiconductor & Display Technology
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• v.4 no.4 s.13
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• pp.27-31
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• 2005

This article contains the development of FPC bonder that used for repair or trial product. Nowadays, in FPO module process (including PDP) accept the thermo-compress bonding method when attach FPC(Flexible Printed Circuit Board), TCP(Tape Carrier Package) and COF(Chip on the FPC) by ACF(Anisotropic Conductive Film). This system consists of ACF attachment part, pre-bonding part, main bonding part, loading / unloading part. This composition is a stand-alone system, not an in-line system. Hereafter, this composition should be developing into in-line system in all area of FPD industry.

• Journal of the Korean Society of Industry Convergence
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• v.25 no.3
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• pp.333-340
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• 2022

Recently, the use of large-capacity secondary batteries for electric vehicles is rapidly increasing, and accordingly, the demand for technologies and equipment for battery reliability evaluation is increasing significantly. The existing short circuit test equipment for evaluating the stability of the existing secondary battery consists of relays, MCs, and switches, so when a large current is energized during a short circuit, contact fusion failures occur frequently, resulting in high equipment maintenance and repair costs. There was a disadvantage that repeated testing was impossible. In this paper, we developed an electronic short circuit test device that realizes stable switching operation when a large-capacity power semiconductor switch is energized with a large current, and applied smart ICT technology to this electronic short circuit stability test system to achieve high speed and high precision through communication with the master. It is expected that the inspection history management system based on data measurement, database format and user interface will be utilized as essential inspection process equipment.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.11a
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• pp.279-280
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• 2008

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.295-296
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• 2006

We developed wire frame drive unit based on SMA for the 3D Shape display. Our basic concept is wire frame combination connected with a chain form which can create various shapes and it compared with pin array mechanism which is not able to display mushroom shape. It imitates antagonist mechanism of human musculoskeletal system. we create similar motion using repair-relaxation mechanism and locking mechanism by SMA. Therefore, in this paper, we propose SMA control solution for actuating repair-relaxation mechanism and locking mechanism. In our control system. we use optical sensor and quantitative angle between wire frames for closed loop control. And we supply amplified current for SMA by circuit composed of transistor and apply PWM signal to circuit for efficient control. So, wire frame drive unit enable diversity angle control based on sensor data. And then combination of wire frame drive units will create various objects.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.5
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• pp.586-592
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• 2018

In this paper, HIC with various functions is proposed for the design 140W LED power control circuit. The proposed HIC integrates constant voltage/constant current circuit, short circuit protection circuit, internal constant voltage circuit, and dimmer circuit, thereby reducing the horizontal length of the PCB by 16% comparing with the conventional system. Through various experiments, we verified the performance of each block implemented inside of HIC with numerical results. (Constant voltage variation ratio: 2.9%, dimmer circuit duty variation within 5%, stable short protection at 720 mA) Since the PCB area can be significantly reduced by applying the proposed HIC. It is possible to reduce the PCB manufacturing time which takes up most of the manufacturing time, however, It is expected that the faulted power module can be replaced without replacing the whole PCB, so that maintenance / repair can be made easier.

• The Journal of Information Technology
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• v.3 no.3
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• pp.57-65
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• 2000

We have proposed BIST method and circuit for embedded 16M SDRAM with logic. It can test the AC parameter of embedded 16M SDRAM using the BIST circuit capable of detecting the address of a fail cell of a 16M SDRAM installed in an Merged Memory with Logic(MML) generating the information of repair for redundancy circuit. The function and AC parameter of the embedded memory can also be tested using the proposed BIST method. The total gate of the BIST circuit is approximately 4,500 in the case of synthesizing by $0.25\mu\textrm{m}$ cell library. and verify the result of Verilog simulation. The test time of each one AC parameter is about 200ms using 2Y-March 14N algorithm.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.501-503
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• 2005

The improvement of load following operation of the thermal power plant is influenced to the electrical quality. Analysis of boiler, turbine, and governor system, and the study of control algorithm are preceded. The thermal power plant is operated by various control systems. In the case of faulty governor system, it takes long days to solve the problem and impossible to repair the mechanism without outage. A non-planned out-age is taken into consideration because of economical power production. In this paper, to clear the continuous swings of an old turbine governor system(YEOSU #1), the trend, the control logic, and the hydraulic mechanism are analyzed, and then the control circuit with ADAPT function and the 1st order lag circuit are inserted and modified. After that, the power plant comes to automatic governor control operation.