• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.455-459
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• 2004

Electrostatic discharge(ESD) is a serious reliability concern. It causes approximately most of all field failures of integrated circuits. Inevitably, future IC technologies will shrink the dimensions of interconnects, gate oxides, and junction depths, causing ICs to be increasingly susceptible to ESD-induced damage [1][2][3]. This thesis shows the optimization of the ESD protection circuit based on the tested results of MM (Machine Model) and HBM (Human Body Model), regardless of existing Reference in fully silicided 0.18 um CMOS process. His thesis found that, by the formation of silicide in a source and drain contact, the dimensions around the contact had a less influence on the ESD robustness and the channel width had a large influence on the ESD robustness [8].

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.139-142
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• 2001

As microeletronics technology continues to progress, there is also a continuous demand on highly integration and miniaturization of systems. For example, it is desirable to package several integrated circuits together in multilayer structure, such as multichip modules, to achieve higher levels of compactness and higher performance. Passive components (i.e., capacitors, resistors, and inductors) are very important for many MCM applications. In addition, the low-temperature co-fired ceramic (LTCC) process has considerable potential for embedding passive components in a small area at a low cost. In this paper, we investigate a method of statistically modeling integrated passive devices from just a small number of test structures. A set of LTCC inductors is fabricated and their scattering parameters (5-parameters) are measured for a range of frequencies from 50MHz to 5GHz. An accurate model for each test structure is obtained by using a building block based modeling methodology and circuit parameter optimization using the HSPICE circuit simulator.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.484-485
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• 2003

We report on the optimization of the fabrication process of hybrid sol-gel thin film deposition to produce low cost $1 {\times} 16$ splitters for optical communications. We learn that sol-gel film thickness is dependent upon the spinning speeds and viscosity of the sol-gel solutions and refractive index upon the dopant concentrations of Al and Zr in the sol solutions. We could find the optimized physical conditions to achieve the desired thickness of core and cladding layers. We will further carry out the fabrication and measurements of insertion loss, polarization dependent loss (PDL), etc. for the performance of fabricated splitter devices.

• Progress in Superconductivity and Cryogenics
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• v.7 no.1
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• pp.17-20
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• 2005

We has designed, fabricated, and measured a Single flux quantum (SFQ) toggle flip-flop (TFF). The TFF is widely used in superconductive digital electronics circuits. Many digital devices, such as frequency counter, counting ADC and program counter be used TFF Specially, a program counter may be constructed based on TFF We have designed the newly TFF and obtained high bias margins on test. In this work, we used two circuit simulation tools, WRspice and Julia, as circuit optimization tools. We used XIC for a layout tool. Newly designed TFF had minimum bias margins of +/- $37\%$ and maximum bias margins of +/-$37\%$(enhanced from +/- $37\%$). The designed circuits were fabricated by using Nb technology The test results showed that the re-optimized TFF operated correctly on 100kHz and had a very wide bias margins of +/- $53\%$.

• Transactions of the Korean Society of Mechanical Engineers
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• v.17 no.12
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• pp.3063-3072
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• 1993

The layout is an important and difficult problem in industrial applications like sheet metal manufacturing, garment making, circuit layout, plant layout, and land development. The module layout problem is known to be non-deterministic polynomial time complete(NP-complete). To efficiently find an optimal layout from a large number of candidate layout configuration a heuristic algorithm could be used. In recent years, a number of researchers have investigated the combinatorial optimization problems by using neural network principles such as traveling salesman problem, placement and routing in circuit design. This paper describes the application of Self-organizing Feature Maps(SOM) of the Kohonen network and Simulated Annealing Algorithm(SAA) to the layout problem of the two-dimensional rectangular shapes.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.2389-2391
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• 2000

To design high quality products at low cost is one of very important tasks for engineers. Design optimization for performances can be one solution in this task. There is the robust design which has been proved effectively in many fields of engineering design. In this paper, the concept of robust design is introduced and combined to the fuzzy optimization method and the fuzzy logic system method with non-singleton. These methods are applied for data analysis to get optimum parameters and to reduce experiments. The optimum parameter set points are obtained by the proposed methods. These methods are applied to a filter circuit, a part of the audio circuit of mobile radio transceiver. The simulation results are compared each other. The new methods reduce and predict the effect of parameter variation sources

• Journal of Korean Society of Industrial and Systems Engineering
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• v.16 no.28
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• pp.1-8
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• 1993

Electrical or electronic products have been becoming smaller and high integrated recently, with printed circuit boards(PCB's) being the key components for these products. The introduction of new technology of surface mounted devices(SMD) opens new ways towards high integration on the PCB. Many plants in eletronical industry which produce high variety of PCB's to meet the demands of customer orders require flexibility in PCB's production lines. This survey paper describes the related optimization problems and solution methods to the automated surface mount technology(SMT) assembly lines, and provides with the research direction for improving flexibility.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.4
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• pp.344-348
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• 2002

As microelectronics technology continues to progress, there is also a continuous demand on highly integration and miniaturization of systems. For example, it is desirable to package several integrated circuits together in multilayer structure, such as multichip modules, to achieve higher levels of compactness and higher performance. Passive components (i.e., capacitors, resistors, and inductors) are very important fort many MCM applications. In addition, the low-temperature co-fired ceramic (LTCC) process has considerable potential for embedding passive components in a small area at a low cost. In this paper, we investigate a method of statistically modeling integrated passive devices from just a small number of test structures. A set of LTCC inductors is fabricated and their scattering parameters (s-parameters) are measured for a range of frequencies from 50MHz to 5GHz. An accurate model for each test structure is obtained by using a building block based modeling methodology and circuit parameter optimization using the HSPICE circuit simulator.

• Journal of Power System Engineering
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• v.10 no.4
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• pp.147-152
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• 2006

The current type amplifier is the device that is used for an actuator as the motor's torque controller. However, it is too difficult to select the parameter value that has the desired output because the current type amplifier's transfer function is too complex. This study concern about the design of the current type amplifier with the desired output. From the modeled transfer function of the current type amplifier, the optimal parameter values of the transfer function can be selected in order to have the desired output using the Real Coded Genetic Algorithm(RCGA). The real circuit is made with the selected parameter value. The step response of the real circuit is in good agreement with the desired step response.

• The KSFM Journal of Fluid Machinery
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• v.16 no.2
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• pp.35-41
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• 2013

Inlet part of a printed circuit heat exchanger has been optimized by using three-dimensional Reynolds-Averaged Navier-Stokes analysis and surrogate modeling techniques. Kriging model has been used as the surrogate model. The objective function for the optimization has been defined as a linear combination of uniformity of mass flow rate and the pressure loss with a weighting factor. For the optimization, the angle of the inlet plenum wall, radius of curvature of the inlet plenum wall, and width of the inlet pipes have been selected as design variables. Twenty six design points are obtained by Latin Hypercube Sampling in design space. Through the optimization, considerable improvement in the objective function has been obtained in comparison with the reference design of PCHE.