• 제목/요약/키워드: Circuit optimization

검색결과 480건 처리시간 0.025초

나선형 자장압축발전기의 코일설계 최적화 (Optimization of Coil Design for Helical Magneto-Cumulative Generators)

  • 국정현;이흥호
    • 대한전기학회논문지:전기기기및에너지변환시스템부문B
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    • 제53권8호
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    • pp.477-487
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    • 2004
  • Helical magneto-cumulative generators(MCGs) are devices which convert explosive energy into electromagnetic energy. The electromagnetic energy supplied from an external circuit is amplified by an explosively driven metal conductor mounted at the center of a helical coil compressing magnetic flux between the conductor and the coil. To optimize the coil design, output properties of small-size helical MCGs were measured while varying design parameters; the number of coil sections, length of the sections, pitch in the sections, and type of copper wire. Dimensions of the coil were kept constant, 50 mm in diameter and 200 mm in length. The coil was fabricated by using enamel-coated copper wire of 1 mm in diameter. The highest energy amplification ratio and figure of merit were 52.5 and 0.81, respectively. from an helical MCG with initial inductance of 63.7 $\mu$H at initial energy of 0.152 kJ Based on the experimental and calculated results, empirical formulas capable of optimizing coil designs were derived. By using these formulas, pitch in each coil section can be obtained at an arbitrary inductive load for high energy amplification ratio and figure of merit.

Optimized Phase Noise of LC VCO Using an Asymmetrical Inductance Tank

  • Yoon Jae-Ho;Shrestha Bhanu;Koh Ah-Rah;Kennedy Gary P.;Kim Nam-Young
    • Journal of electromagnetic engineering and science
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    • 제6권1호
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    • pp.30-35
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    • 2006
  • This paper describes fully integrated low phase noise MMIC voltage controlled oscillators(VCOs). The Asymmetrical Inductance Tank VCO(AIT-VCO), which optimize the shortcoming of the previous tank's inductance optimization approach, has lower phase noise performance due to achieving higher equivalent parallel resistance and Q value of the tank. This VCO features an output power signal in the range of - 11.53 dBm and a tuning range of 261 MHz or 15.2 % of its operating frequency. This VCO exhibits a phase noise of - 117.3 dBc/Hz at a frequency offset of 100 kHz from carrier. A phase noise reduction of 15 dB was achieved relative to only one spiral inductor. The AIT-VCO achieved low very low figure of merit of -184.6 dBc/Hz. The die area, including buffers and bond pads, is $0.9{\times}0.9mm^2$.

전자식 레이더 반사기를 위한 X-band 마이크로웨이브 증폭기 설계 및 구현 (Design and fabrication of the X-band microwave amplifier for Electronic Radar Reflector)

  • 정종혁;양규식
    • 한국정보통신학회논문지
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    • 제2권3호
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    • pp.275-282
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    • 1998
  • 본 연구에서는 X밴드 전자식 레이더 반사기에 사용하기 위한 마이크로웨이브 5단 전력증폭기를 평형증폭기 구조를 이용하여 설계하고 제작하였다. 사용한 기판은 FR4이고, 사용한 소자는 FHX35LG, FLK012WF와 FLK022WG이다. 회로의 설계와 최적화는 마이크로웨이브 CAD 프로그램인 CNL/2를 사용하였다. 설계한 주파수 대역에서 측정된 결과는 46dB의 이득과 -14.2dB의 입력반사손실, -16.6dB의 출력반사손실을 나타내며, IM$_3$은 32dBc였다. 측정 결과는 시뮬레이션 결과와 거의 일치하였다.

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Modeling of Lithium Battery Cells for Plug-In Hybrid Vehicles

  • Shin, Dong-Hyun;Jeong, Jin-Beom;Kim, Tae-Hoon;Kim, Hee-Jun
    • Journal of Power Electronics
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    • 제13권3호
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    • pp.429-436
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    • 2013
  • Online simulations are utilized to reduce time and cost in the development and performance optimization of plug-in hybrid electric vehicle (PHEV) and electric vehicles (EV) systems. One of the most important factors in an online simulation is the accuracy of the model. In particular, a model of a battery should accurately reflect the properties of an actual battery. However, precise dynamic modeling of high-capacity battery systems, which significantly affects the performance of a PHEV, is difficult because of its nonlinear electrochemical characteristics. In this study, a dynamic model of a high-capacity battery cell for a PHEV is developed through the extraction of the equivalent impedance parameters using electrochemical impedance spectroscopy (EIS). Based on the extracted parameters, a battery cell model is implemented using MATLAB/Simulink, and charging/discharging profiles are executed for comparative verification. Based on the obtained results, the model is optimized for a high-capacity battery cell for a PHEV. The simulation results show good agreement with the experimental results, thereby validating the developed model and verifying its accuracy.

가동 자석형 3 축 구동 엑츄에이터 개발 (Development of 3-axis Moving Magnet Type Actuator)

  • 송명규;허영준;박노철;유정훈;박영필
    • 정보저장시스템학회논문집
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    • 제3권4호
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    • pp.191-195
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    • 2007
  • The optical disc drive has used a high NA objective lens and a shorter wavelength laser diode for high recording density. But high NA and shorter wavelength cause several margins to become short. Focusing and tracking servo has to be more accurate and active tilt compensation mechanism is also needed for coma aberration compensation. In this paper, we proposed 3-axis moving magnet type actuator. For 3-DOF motion, moving coil actuator has to be equipped with 6 wires for supplying 3 independent signals. However, moving magnet type actuator doesn't need to change the configuration of wires because coils are in stator. So, we added a tilt mechanism to the 2-axis moving magnet actuator which is designed in previous research. Addition of the tilt mechanism cuts down the focus sensitivity. So, maximization the tilting sensitivity and securing the focusing sensitivity are objectivities of this research. DOE (design of experiments) procedures of electromagnetic circuit are performed for parameter study and the optimization is also performed to maximize the tilt sensitivity. And then the final design is suggested and its performance is verified by FE simulation.

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고정입자 패드를 이용한 텅스텐 CMP에 관한 연구 (The Study of Metal CMP Using Abrasive Embedded Pad)

  • 박재홍;김호윤;정해도
    • 한국정밀공학회지
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    • 제18권12호
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    • pp.192-199
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    • 2001
  • Chemical mechanical planarization (CMP) has emerged as the planarization technique of choice in both front-end and back-end integrated circuit manufacturing. Conventional CMP process utilize a polyurethane polishing pad and liquid chemical slurry containing abrasive particles. There hale been serious problems in CMP in terms of repeatability and deflects in patterned wafers. Especial1y, dishing and erosion defects increase the resistance because they decrease the interconnection section area, and ultimately reduce the lifetime of the semiconductor. Methods to reduce dishing & erosion have recently been interface hardness of the pad, optimization of the pattern structure as dummy patterns. Dishing & erosion are initially generated an uneven pressure distribution in the materials. These defects are accelerated by free abrasives and chemical etching. Therefore, it is known that dishing & erosion can be reduced by minimizing the abrasive concentration. Minimizing the abrasive concentration by using CeO$_2$is the best solution for reducing dishing & erosion and for removal rate. This paper introduce dishing & erosion generating mechanism and a method fur developing a semi-rigid abrasive pad to minimize dishing & erosion during CMP.

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Design optimization of GaN diode with p-GaN multi-well structure for high-efficiency betavoltaic cell

  • Yoon, Young Jun;Lee, Jae Sang;Kang, In Man;Lee, Jung-Hee;Kim, Dong-Seok
    • Nuclear Engineering and Technology
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    • 제53권4호
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    • pp.1284-1288
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    • 2021
  • In this work, we propose and design a GaN-based diode with a p-doped GaN (p-GaN) multi-well structure for high efficiency betavoltaic (BV) cells. The short-circuit current density (JSC) and opencircuit voltage (VOC) of the devices were investigated with variations of parameters such as the doping concentration, height, width of the p-GaN well region, well-to-well gap, and number of well regions. The JSC of the device was significantly improved by a wider depletion area, which was obtained by applying the multi-well structure. The optimized device achieved a higher output power density by 8.6% than that of the conventional diode due to the enhancement of JSC. The proposed device structure showed a high potential for a high efficiency BV cell candidate.

Efficient Decoupling Capacitor Optimization for Subsystem Module Package

  • Lim, HoJeong;Fuentes, Ruben
    • 마이크로전자및패키징학회지
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    • 제29권1호
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    • pp.1-6
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    • 2022
  • The mobile device industry demands much higher levels of integration and lower costs coupled with a growing awareness of the complete system's configuration. A subsystem module package is similar to a board-level circuit that integrates a system function in a package beyond a System-in-Package (SiP) design. It is an advanced IC packaging solution to enhance the PDN and achieve a smaller form factor. Unlike a system-level design with a decoupling capacitor, a subsystem module package system needs to redefine the role of the capacitor and its configuration for PDN performance. Specifically, the design of package's form factor should include careful consideration of optimal PDN performance and the number of components, which need to define the decoupling capacitor's value and the placement strategy for a low impedance profile with associated cost benefits. This paper will focus on both the static case that addresses the voltage (IR) drop and AC analysis in the frequency domain with three specific topics. First, it will highlight the role of simulation in the subsystem module design for the PDN. Second, it will compare the performance of double-sided component placement (DSCP) motherboards with the subsystem module package and then prove the advantage of the subsystem module package. Finally, it will introduce three-terminal decoupling capacitor (decap) configurations of capacitor size, count and value for the subsystem module package to determine the optimum performance and package density based on the cost-effective model.

SPECK 양자 회로 최적화를 통한 양자 후 보안 강도 평가 (Post-Quantum Security Evaluation Through SPECK Quantum Circuit Optimization)

  • 장경배;엄시우;송경주;양유진;서화정
    • 한국정보처리학회:학술대회논문집
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    • 한국정보처리학회 2021년도 추계학술발표대회
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    • pp.243-246
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    • 2021
  • 양자 알고리즘이 수행 가능한 양자 컴퓨터는 기존 암호 시스템의 보안성을 낮추거나 깨뜨릴 수 있다. 이에 양자 컴퓨터의 공격 관점에서 기존 암호 시스템의 보안성을 재평가하는 연구들이 활발히 수행되고 있다. NIST는 대칭키 암호 시스템에 대한 양자 후 보안 강도에 평가에 Grover 알고리즘의 적용 비용을 채택하고 있다. Grover 알고리즘이 대칭키 암호 시스템의 보안성을 절반으로 줄일 수 있는 시점에서 중요한 건 공격 비용이다. 본 논문에서는 경량블록암호 SPECK 양자 회로 최적화 구현을 제시한다. ARX 구조의 SPECK에 대해 최적의 양자 덧셈기를 채택하고 병렬 덧셈을 수행한다. 그 결과, 최신 구현물과 비교하여 depth 측면에서 56%의 성능향상을 제공한다. 최종적으로, 제시하는 SPECK 양자 회로를 기반으로 Grover 알고리즘 적용 비용을 추정하고 양자 후 보안 강도를 평가한다.

고출력 무전극램프의 점등회로 설계를 통한 특성분석 및 최적화에 관한 연구 (A Study on the characteristic analysis and optimization according to Ballast design of Induction Lamp)

  • 정영일;정대철;박대희;김용갑
    • 한국정보전자통신기술학회논문지
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    • 제10권1호
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    • pp.31-37
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    • 2017
  • 본 논문에서는 고출력 무전극 램프 시스템 개발에서 램프 내에 가스종류, 혼합비, 압력과 방전관 사이즈, 아말감종류 및 혼합비, 페라이트코어의 특성등의 최적화를 통한 램프 설계 부분을 연구하였다. 또한 구동방식에 따른 점등회로의 역율 및 효율개선, 파형이나 인가 주파수에 따른 특성 분석을 통한 점등회로설계 부분 등을 고려하였으며, 최종적으로 주변 환경을 고려 무전극 등기구 설계를 수행 하였다. 고출력 무전극 램프용 점등회로의 설계를 통한 특성분석을 진행하여 개선 보완을 통하여 효울을 향상 시켰으며 점등회로의 구동주파수에 따른 무전극 램프의 광학적 특성 및 시스템 영향을 확인한 결과, $7{\sim}10^{\circ}C$ 정도 낮은 특성의 135kHz로 구동하는 점등회로를 최적화하였다. 실험적으로 Peak Noise 발생으로 인한 FET(Q3,Q4) demage 현상을 개선하였다. 최종적으로 무전극램프용 점등회로 최종 설계도을 통해 약 2~3배 이상의 수명을 확보함으로써 안정기의 신뢰성 및 무전극 램프 시스템의 효율이 높음을 알 수 있었다.