• 제목/요약/키워드: Circuit optimization

검색결과 480건 처리시간 0.024초

Mo:Na 두께에 따른 Cu(In,Ga)Se2 박막의 물성과 효율변화 (The Physical Properties and Efficiencies of Cu(In,Ga)Se2 Thin Films Depending on the Mo:Na Thickness)

  • 신윤학;김명한
    • 한국재료학회지
    • /
    • 제24권3호
    • /
    • pp.123-128
    • /
    • 2014
  • To realize high-performance thin film solar cells, we prepared CIGS by the co-evaporation technique on both sodalime and Corning glass substrates. The structural and efficient properties were investigated by varying the thickness of the Mo:Na layer, where the total thickness of the back contact was fixed at 1${\mu}m$. As a result, when the Mo:Na thickness was 300 nm on soda-lime glass, the measured Na content was 0.28 %, the surface morphology was a plate-like compact structure, and the crystallinity by XRD showed a strong peak of (112) preferential orientation together with relatively intense (220) and (204) peaks as the secondary phases influenced crystal formation. In addition, the substrates on soda-lime glass effected the lowest surface roughness of 2.76 nm and the highest carrier density and short circuit current. Through the optimization of the Mo:Na layer, a solar conversion efficiency of 11.34% was achieved. When using the Corning glass, a rather low conversion efficiency of 9.59% was obtained. To determine the effects of the concentration of sodium and in order to develop a highefficiency solar cells, a very small amount of sodium was added to the soda lime glass substrate.

실내 온열환경 제어를 위한 PMV 센서의 개발 및 적용성 평가연구 (Development and Evaluation of a PMV Sensor for the Control of Indoor Thermal Environment)

  • 윤동원;강효석;안병욱
    • 설비공학논문집
    • /
    • 제15권10호
    • /
    • pp.870-878
    • /
    • 2003
  • The maintenance of thermal equilibrium between the human body and its environment is one of the primary requirements for health, wellbeing and comfort. For the effective control of indoor thermal environment, thermostat or humidistat is used. But, it is not sufficient to control the indoor thermal environment using only one or two parameters as human response for the indoor comfortable environment. So an environmental thermal index is required for the control of indoor thermal environment effectively. In this study, a PMV sensor has been developed which has integrated from various kinds of individual sensors for temperature, humidity, air velocity, radiant temperature. After applying the PMV and PPD equation, it is possible to monitor the indoor thermal environment with the sensor system, which is adopted to the circuit for optimization according to the human response with the metabolic rate and activities. The measurement was carried out to verify the performance of the integrated sensor system in comparison with existing measurement system, the PMV meter. As a result, the possibility of applying the PMV sensor to control the indoor thermal environment simultaneously was examined.

BGA to CSP to Flip Chip - Manufacturing Issues

  • Caswell, Greg;Partridge, Julian
    • 한국마이크로전자및패키징학회:학술대회논문집
    • /
    • 한국마이크로전자및패키징학회 2001년도 Proceedings of 6th International Joint Symposium on Microeletronics and Packaging
    • /
    • pp.27-34
    • /
    • 2001
  • The BGA Package has been the area array package of choice for several rears. Recently, the transition has been to finer pitch configuration called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch, requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and piece equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

  • PDF

데이터시트 기반의 새로운 PSIM 태양광 모델 (A New PSIM Model for PV Panels Employing Datasheet-based Parameter Tuning)

  • 박준영;최성진
    • 전력전자학회논문지
    • /
    • 제20권6호
    • /
    • pp.498-508
    • /
    • 2015
  • In the simulation of photovoltaic (PV) power conditioning systems, PSIM is a widely accepted circuit simulation platform because of its fast speed and C-code support. PSIM provides two kinds of generic PV panel models: functional model and physical model. Whereas the functional model simulates PV in the standard test condition (STC) only, the physical model can emulate changing PV characteristics under varying temperatures and irradiation conditions and is thus more suitable for system simulation. However, the physical model requires complicated parameters from users, and thus it is prone to errors and is difficult to use. In this study, a new PSIM model for PV is presented to solve these problems. The proposed model utilizes manufacturers' datasheet values specified under STC only and excludes user-defined information from input parameters. To achieve good accuracy even in varying environmental conditions, single-diode model parameters are successively tuned to a time-varying virtual datasheet. Comparison with a conventional physical model shows that the proposed model provides more accurate simulation according to error analysis based on the EN50530 standard.

53.1 Low power and low EMI display technologies based on the total image systematic approach

  • Okumura, Haruhiko;Baba, Masahiro;Takagi, Ayako;Sasaki, Hisashi;Matsuba, Mitsunori
    • 한국정보디스플레이학회:학술대회논문집
    • /
    • 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
    • /
    • pp.1081-1085
    • /
    • 2009
  • We have already developed EMI reducing techniques using lossless compression by vertically differential EMI suppression method (VDE[1]). It applies lossless modulo reduction and data bit mapping optimization for low voltage differential signaling (LVDS) transmission lines, that reduces the probability of transient bit and EMI by 12 dB [6][7]. We also improved and optimized the VDE for low power LCD interface. With this modified VDE algorithm[8], the developed FPGA was measured the reduction of the power consumption of LCD circuit by more than 15 % compared to the conventional methods in the case of 14-in LCD with SXGA resolution. The VDE algorithm is based on the total image systematic approach. In the VDE method, the present image signals are subtracted for the 1H delayed image signals and transferred to a column driver through a PCB. As the vertical correlations for image signals are very high, we expected that most of the vertically subtracted image signals remain 0 level and transient cycles become very long. As a result, the power consumption and EMI are extremely reduced for the transferred image signals on a PCB. In this paper, we discussed our proposed method by emphasizing the fact that systematic approach are important based on not only display point of view but also total system point of view.

  • PDF

CDMA 하향링크의 간섭제거를 위한 새로운 다계층 신경망의 복잡도 개선에 관한 연구 (Simplified Multilayer Perceptron for Interference Cancellation of CDMA Forward Link)

  • 이봉희;김종민;이상규;한영수;황인관
    • 한국통신학회논문지
    • /
    • 제28권3C호
    • /
    • pp.271-278
    • /
    • 2003
  • 본 논문에서는 CDMA 하향링크에서 최적화가 용이한 새로운 다층 신경망을 제안하고 이를 적용한 신경망 수신기를 레이크 수신기와 비교하여 CDMA 하향링크에서 간섭이 제거되어 성능이 개선되었음을 입증하였다. 새로운 다층신경망은 기존의 다층신경망에 비해 시스템 복잡도가 개선되고 최적화가 용이하면서 기존의 다층신경망과 동일한 간섭제거에 의한 성능 향상 효과를 얻을 수 있어 실제 시스템에 적용하기에 적합하다. CDMA 하향링크에서 요구되는 고속의 데이터 전송을 위해 BLAST를 시작으로 STS, STTC, STC 등 다양한 STD 기술들이 제시되었으나 타사용자의 정보부재로 다중사용자 검파가 불가하고 충분한 수의 안테나를 장착할 수 없는 하향링크의 한계로 실질적으로 채널효율증대 효과가 미흡한 실정이다. [10]-[15]이러한 문제점을 해결하기 위하여 복잡한 채널환경에 대해 적응능력이 뛰어나고, 고속의 병렬처리의 장점을 갖으며, 실시간 구현이 용이한 최적화된 단계층 신경망을 이용해서 다중사용자 간섭을 제거하였다. 여기에 STC 기술들을 접목시킨다면 CDMA 단말기의 획기적인 채널효율증대 가능성을 기대할 수 있을 것이다.

Optimization of Material and Process for Fine Pitch LVSoP Technology

  • Eom, Yong-Sung;Son, Ji-Hye;Bae, Hyun-Cheol;Choi, Kwang-Seong;Choi, Heung-Soap
    • ETRI Journal
    • /
    • 제35권4호
    • /
    • pp.625-631
    • /
    • 2013
  • For the formation of solder bumps with a fine pitch of 130 ${\mu}m$ on a printed circuit board substrate, low-volume solder on pad (LVSoP) technology using a maskless method is developed for SAC305 solder with a high melting temperature of $220^{\circ}C$. The solder bump maker (SBM) paste and its process are quantitatively optimized to obtain a uniform solder bump height, which is almost equal to the height of the solder resist. For an understanding of chemorheological phenomena of SBM paste, differential scanning calorimetry, viscosity measurement, and physical flowing of SBM paste are precisely characterized and observed during LVSoP processing. The average height of the solder bumps and their maximum and minimum values are 14.7 ${\mu}m$, 18.3 ${\mu}m$, and 12.0 ${\mu}m$, respectively. It is expected that maskless LVSoP technology can be effectively used for a fine-pitch interconnection of a Cu pillar in the semiconductor packaging field.

VLSI 테스트 이론을 이용한 Global Redundancy 조사 (Global Redundancey Check by VLSI Test Theory)

  • 이성봉;정정화
    • 대한전자공학회논문지
    • /
    • 제26권4호
    • /
    • pp.138-144
    • /
    • 1989
  • 본 논문에서는 게이트레벨회로 최적화를 위한, 논리적 redundancy를 제거하는 새로운 방법을 제안한다. 본 방법은 회로내의 모든 신호선에 대한 redundancy 조사를 피하여 일부의 신호선-fanout branch 신호선에 한정하여 조사를 행한다. 또 조사한 신호선이 nonredundant 할 경우에는, 그 신호선에 대한 조사 과정에 생성된 정보만을 이용하여, 다른 nonrodundant한 신호선을 유효하는 효율적인 procedure을 사용한다. 그리고, 한 신호선에 대한 redundancy 재조사를 피하기 위해, 신호선의 조사순서를 결정하는 휴리스틱한 방법을 제안한다. 본 방법은 기존의 테스팅이론을 응용한 휴리스틱한 방법으로, 각 신호선에 대한 redundancy 재조사를 행하지 않기 때문에 기존의 방법에 비해 실행시간이 매우 빠르다.

  • PDF

리튬폴리머 배터리 잔존충전용량 추정을 위한 비선형 관측기 설계 (A Nonlinear Observer Design for Estimating State-of-Charge of Lithium Polymer Battery)

  • 류석환
    • 한국지능시스템학회논문지
    • /
    • 제22권3호
    • /
    • pp.300-304
    • /
    • 2012
  • 본 논문은 리튬 폴리머 배터리 셀의 잔존충전용량을 추정하기 위한 비선형 관측기의 설계방법을 제시한다. 배터리 셀의 동적방정식은 비선형 전압원을 갖는 간단한 RC 전기회로로 모델하고 파라메터는 비선형 최적화기법을 이용하여 구한다. 관측기 이득은 제곱합 분해기법을 사용하여 오차의 동적방정식이 점근적으로 안정하고 추정오차 감소율이 설계자가 지정한 값 이하가 되도록 설계한다. 관측기의 성능을 입증하기 위하여 UDDS 전류 프로파일을 사용한 실험 데이터를 이용하여 모의실험을 수행하였다.

Power-Efficient Rate Allocation of Wireless Access Networks with Sleep-Operation Management for Multihoming Services

  • Lee, Joohyung;Yun, Seonghwa;Oh, Hyeontaek;Newaz, S.H. Shah;Choi, Seong Gon;Choi, Jun Kyun
    • Journal of Communications and Networks
    • /
    • 제18권4호
    • /
    • pp.619-628
    • /
    • 2016
  • This paper describes a theoretical framework for rate allocation to maximize the power efficiency of overall heterogeneous wireless networks whose users are assumed to have multihoming capabilities. Therefore, the paper first presents a power consumption model considering the circuit power and radio transmission power of each wireless network. Using this model, two novel power efficient rate allocation schemes (PERAS) for multihoming services are proposed. In this paper, the convex optimization problem for maximizing the power efficiency over wireless networks is formulated and solved while guaranteeing the required quality of service (QoS). Here, both constant bit rate and variable bit rate services are considered. Furthermore, we extend our theoretical framework by considering the sleep-operation management of wireless networks. The performance results obtained from numerical analysis reveal that the two proposed schemes offer superior performance over the existing rate allocation schemes for multihoming services and guarantee the required QoS.