• Title/Summary/Keyword: Circuit optimization

Search Result 480, Processing Time 0.023 seconds

A Systematic Power Factor Improvement Method for an Electro Acoustic Transducer with Low Coupled Dual Resonances (상호 결합이 적은 두 개의 공진점을 갖는 광대역 전기 음향 변화기를 위한 역률 개선 회로 설계 방법 연구)

  • Lim, Jun-Seok;Pyeon, Yong-Guk
    • The Journal of the Acoustical Society of Korea
    • /
    • v.31 no.7
    • /
    • pp.480-486
    • /
    • 2012
  • In the design of electro acoustic transducer, power factor improvement circuit is more required rather than impedance matching if the driving power amplifier has little inner resistance. Many research results have been focused on the power matching circuit designing for transferring maximum power in the wideband. There are few results in the designing study on the power factor improvement for the wide band electro acoustic transducer. In this paper, we propose a new design method on the power factor improvement for the wide band electro acoustic transducer. The proposed method consists of two steps, the chebyschev matching method and the constrained optimization, respectively.

Circular Holes Punched in a Magnetic Circuit used in Microspeakers to Reduce Flux Leakage

  • Xu, Dan-Ping;Jiang, Yuan-Wu;Lu, Han-Wen;Kwon, Joong-Hak;Hwang, Sang-Moon
    • Journal of Magnetics
    • /
    • v.21 no.3
    • /
    • pp.387-392
    • /
    • 2016
  • Lower flux leakage designs have become important in the development of microspeakers used in thin and miniaturized mobile phones. We propose four methods to reduce the flux leakage of the magnetic circuit in a microspeaker. Optimization was performed based on the proposed approach by using the response surface method. Electromagnetic analyses were conducted using the finite element method. Experimental results are in good agreement with the simulated results obtained in one degree-of-freedom analysis from 100 to 5 kHz. Both the simulated and experimental results confirm that one of the proposed methods is much more effective in reducing flux leakage than the other methods. In the optimized method, compared with a default approach, the average radial flux density in the air gap decreased only by 5.5%, the maximum flux leakage was reduced by 28.6%, and the acoustic performance at primary resonance decreased by 0.45 dB, which gap is indiscernible to the human ear.

Calculation of Electrodynamic Repulsion Force in Molded Case Circuit Breakers Using the 3-D Finite Element Analysis (3차원 유한요소 해석을 이용한 배선용 차단기의 전자반발력 계산)

  • Kim, Yong-Gi;Park, Hong-Tae;Song, Jung-Chun;Seo, Jung-Min;Degui, Chen
    • Proceedings of the KIEE Conference
    • /
    • 2003.10b
    • /
    • pp.137-140
    • /
    • 2003
  • To the optimization design of molded case circuit breakers(MCCBs), it is necessary and important to calculate the electro-dynamic repulsion force acting on the movable conductor. With 3-D finite element nonlinear analysis, according to the equations among current-magnetic field-repulsion force and taking into account the ferromagnet, contact bridge model is introduced to simulate the current constriction between contacts, so Lorentz and Holm force acting on the movable conductor and contact, respectively, can be integrated to calculate. Coupled with circuit equations, the opening time of movable contact also can be obtained using iteration with the restriction of contact force. Simulation and experiment for repulsion forte and opening time of five different configuration models have been investigated. The results indicate that the proposed method is effective and capable of evaluating new design of contact systems in MCCBs.

  • PDF

The Impact of Gate Leakage Current on PLL in 65 nm Technology: Analysis and Optimization

  • Li, Jing;Ning, Ning;Du, Ling;Yu, Qi;Liu, Yang
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.12 no.1
    • /
    • pp.99-106
    • /
    • 2012
  • For CMOS technology of 65 nm and beyond, the gate leakage current can not be negligible anymore. In this paper, the impact of the gate leakage current in ring voltage-controlled oscillator (VCO) on phase-locked loop (PLL) is analyzed and modeled. A voltage -to-voltage (V-to-V) circuit is proposed to reduce the voltage ripple on $V_{ctrl}$ induced by the gate leakage current. The side effects induced by the V-to-V circuit are described and optimized either. The PLL design is based on a standard 65 nm CMOS technology with a 1.8 V power supply. Simulation results show that 97 % ripple voltage is smoothed at 216 MHz output frequency. The RMS and peak-to-peak jitter are 3 ps and 14.8 ps, respectively.

Design Automation of High-Performance Operational Amplifiers (고성능 연산 증폭기의 설계 자동화)

  • Yu, Sang-Dae
    • Journal of Sensor Science and Technology
    • /
    • v.6 no.2
    • /
    • pp.145-154
    • /
    • 1997
  • Based on a new search strategy using circuit simulation and simulated annealing with local search, a technique for design automation of high-performance operational amplifiers is proposed. For arbitrary circuit topology and performance specifications, through discrete optimization of a cost function with discrete design variables the design of operational amplifiers is performed. A special-purpose circuit simulator and some heuristics are used to reduce the design time. Through the design of a low-power high-speed fully differential CMOS operational amplifier usable in smart sensors and 10-b 25-MS/s pipelined A/D converters, it has been demonstrated that a design tool developed using the proposed technique can be used for designing high-performance operational amplifiers with less design knowledge and less design effort.

  • PDF

Vision chip for edge detection with resolution improvement through simplification of unit-pixel circuit (단위 픽셀 회로의 간소화를 통해서 해상도를 향상시킨 이차원 윤곽 검출용 시각칩)

  • Sung, Dong-Kyu;Kong, Jae-Sung;Hyun, Hyo-Young;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
    • /
    • v.17 no.1
    • /
    • pp.15-22
    • /
    • 2008
  • When designing image sensors including a CMOS vision chip for edge detection, resolution is a significant factor to evaluate the performance. It is hard to improve the resolution of a bio-inspired CMOS vision using a resistive network because the vision chip contains many circuits such as a resistive network and several signal processing circuits as well as photocircuits of general image sensors such as CMOS image sensor (CIS). Low resolution restricts the use of the application systems. In this paper, we improve the resolution through layout and circuit optimization. Furthermore, we have designed a printed circuit board using FPGA which controls the vision chip. The vision chip for edge detection has been designed and fabricated by using $0.35{\mu}m$ double-poly four-metal CMOS technology, and its output characteristics have been investigated.

Design of RF Receiver using Independent-Gate-Mode Double-Gate MOSFET (Independent-Gate-Mode Double-Gate MOSFET을 이용한 RF Receiver 설계)

  • Jeong, Na-Rae;Kim, Yu-Jin;Yun, Ji-Sook;Park, Sung-Min;Shin, Hyung-Soon
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.46 no.10
    • /
    • pp.16-24
    • /
    • 2009
  • Independent-gate-mode double-gate(IGM-DG) MOSFET overcomes the limitation of 3-terminal device structure, and enables to operate with different voltages for front-gate and back-gate. Therefore, circuit designs becomes not only simple, but also area-efficient due to the controllability of the 4th terminal provided by IGM-DG MOSFETs. In this paper, an RF receiver utilizing IGM-DG MOSFETs is presented and also, the circuit performance is verified by the HSPICE simulations. Besides, the circuit analysis and optimization are performed for various IGM-DG characteristics.

The Stabilization Model of Receive Sensitivity of Thick Film Oscillation Circuit for Air Explosion Shell (공중폭발 탄용 후막 발진회로의 수신감도 안정화 모델)

  • Lim, Young-Cheol;Kim, Kwan-Woo;Choi, Jin-Bong;Jung, Young-Gook
    • The Transactions of the Korean Institute of Power Electronics
    • /
    • v.15 no.1
    • /
    • pp.17-26
    • /
    • 2010
  • This paper proposes the stabilization modelling method of receive sensitivity of thick film oscillation circuit for air explosion shell. The proposed method minimizes the errors of the thick film oscillator which uses air explosion shell for military and it is very similar to the simulation for maximizing the efficiency. Firstly, the proposed method gets the equation of new form through statistical analysis from the data which shows always fixed and stabilized output from the real model. Secondly, the simulation is designed which is possible to predict the output, after optimization that is a model to match the each electronic component output by the equation. In a conclusion, the usefulness, the accuracy and the precision are proved as compared with the output data of real model.

The Optimization of Current Mode CMOS Multiple-Valued Logic Circuits (전류구동 CMOS 다치 논리 회로설계 최적화연구)

  • Choi, Jai-Sock
    • Journal of the Institute of Convergence Signal Processing
    • /
    • v.6 no.3
    • /
    • pp.134-142
    • /
    • 2005
  • The implementation of Multiple-Valued Logic(MVL) based on Current-Mode CMOS Logic(CMCL) circuits has recently been achieved. In this paper, four-valued Unary Multiple-Valued logic functions are synthesized using current-mode CMOS logic circuits. We properly make use of the fact that the CMCL addition of logic values represented using discrete current values can be performed at no cost and that negative logic values are readily available via reversing the direction of current flow. A synthesis process for CMCL circuits is based upon a logically complete set of basic elements. Proposed algorithm results in less expensive realization than those achieved using existing techniques in terms of the number of transistors needed. As an alternative to the cost-table techniques Universal Unary Programmable Circuit (UUPC) for a unary function is also proposed.

  • PDF

Analysis of an Interior Permanent-Magnet Machines with an Axial Overhang Structure based on Lumped Magnetic Circuit Model

  • Seo, Jangho;Seo, Jung-Moo
    • Journal of Magnetics
    • /
    • v.21 no.1
    • /
    • pp.94-101
    • /
    • 2016
  • This paper shows a new magnetic field analysis of an interior permanent magnet (IPM) machines with an axial overhang structure wherein the rotor axial length exceeds that of the stator. The rotor overhang used to increase torque density of the radial flux machine is difficult to analyze because of extra consideration of axial direction, and thus it is general for machine designer to take 3-D finite element analysis (FEA) capable of considering both radial and axial complicated geometry in the machine. However, it requires too much computing time for preliminary design especially for optimization process. Therefore, in this paper a 2-D analytic method using a lumped magnetic circuit model (LMCM) is proposed to overcome the problem. For the analysis of overhang effect, the magnetic circuit is separated and solved from overhang and non-overhang regions respectively. For the validation of proposed concept, 3-D finite element analysis (FEA) is performed. From the analysis results, it is shown that our new proposed method presents good performance in terms of calculating electromotive force (EMF) and torque within a short time. Therefore, the proposed model can be useful in design of IPM with an overhang structure.