• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.376-382
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• 2014

In this paper, a 9-bit 1GS/s high precision folding A/D converter with a 45 nm CMOS technology is proposed. In order to improve the asymmetrical boundary condition error of a conventional folding ADC, a novel scheme with an odd number of folding blocks is proposed. Further, a new digital encoding technique is described to implement the odd number of folding technique. The proposed ADC employs a digital error correction circuit to minimize device mismatch and external noise. The chip has been fabricated with 1.1V 45nm Samsung CMOS technology. The effective chip area is $2.99mm^2$ and the power dissipation is about 120 mW. The measured result of SNDR is 45.35 dB, when the input frequency is 150 MHz at the sampling frequency of 1 GHz. The measured INL is within +7 LSB/-3 LSB and DNL is within +1.5 LSB/-1 LSB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.8 no.1
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• pp.52-60
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• 1997

A 23GHz 2-stage LNA was designed using MPIE numerical analysis and microwave CAD EEsof softwares. The basic circuit was designed by EEsof tools but analyzed more precisely using numerical MPIE tools and modified. The matching sections of the input and output terminals were designed with paralledl coupled filter-type lines, these matching sections perform impedance matching and DC blocking, more over have the advantages of small discontinuities and small errors in the design process. The FET chip is directly attached to the ground metal. The designed LNA gives 15.2dB gain and 2.7dB noise figure. without considering 1.8dB loss of connectors. These results validate our design process and matching schemes and fabrication technologies over the 20GHz frequency range.

• Aerospace Engineering and Technology
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• v.5 no.2
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• pp.67-76
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• 2006

This paper describes the analysis method to define the system specification for conducted EMI environment and verification method to evaluate the conducted EMI performance. Conducted EMI environment is characterized by the electrical power subsystem which is mainly issued by the switching circuit noise, common ground impedance coupling. To define and control these EMI problems, EMI assesment through system analysis are preceded at the early design phase and then EMI reduction methods are applied during the unit/system development phase. System EMC should be carefully controlled and designed in the consideration of EMC safety margin and its performance is fully evaluated at the whole development period.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.3
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• pp.6-11
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• 2006

This paper describes the novel control techniques design of VSC(Voltage Sag Corrector) for the purpose of power line quality enhancement. A fast detecting technique of voltage sag is implemented through the detection of instantaneous value on synchronous rotating dq-reference frame. The first order digital filter is added in the detection algorithm to protect the insensitive characteristics against the noise. The relationship between the total detection time and cut-off frequency of the filter is described. The size of the capacitor bank used as the energy storage element is designed from the point of view of input/output energy with circuit analysis. Finally, the validity of the proposed scheme is proven through the simulated results.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.3
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• pp.603-608
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• 2016

Encoding means converting or processing form or format of information into the other forms to standardize, secure, improve processing speed, store saving spaces and etc. Also, Encoding is converting the information so as to do transmit other form on the sender's information to the receiver in Information-Communication. The device that is conducting the processing is called the encoder. In this dissertation, proposes an encoder of the most basic 4-to-2 encoder. proposed encoder consists of two OR-gate and the proposed structure designs and optimize the spacing of the cell for the purpose of minimizing noise between wiring. Through QCADesigner conducts simulation of the proposed encoder and analyzes the results confirm the effectiveness.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1506-1511
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• 2004

The error control of digital transmission system is a very important subject because of the noise effects, which is very sensitive to transmission performance of the digital communication system It employs a modified Euclid's algorithm to compute the error-location polynomial and error-magnitude polynomial of input data. The circuit size is reduced by selecting the Modified Euclid's Algorithm with one Euclid Cell of mutual operation. And the operation speed of Decoder is improved by using ROM and parallel structure. The proposed Encoder and Decoder are simulated with ModelSim and Active-HDL and synthesized with Synopsys. We can see that this chip is implemented on Xilinx Virtex2 XC2V3000. A share of slice is 28%. nut speed of this paper is 45Mhz.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.5
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• pp.831-835
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• 2016

In this paper, a dual-channel feed-forward transimpedance(TIA) array is realized in a standard $0.18-{\mu}m$ CMOS technology which exploits automatic gain control function to provide 40-dB input dynamic range for either detecting targets nearby or sensing imminent danger situations. Compared to the previously reported conventional feed-forward TIA, the proposed automatic-gain-control feed-forward TIA(AFF-TIA) extends the input dynamic range 25 dB wider by employing a 4-level automatic gain control circuit. Measured results demonstrate the linearly varying transimpedance gain of 47 to $72dB{\Omega}$, input dynamic range of 1:100, the bandwidth of $${\geq_-}670MHz$$, the equivalent input referred noise current spectral density of 6.9 pA/${\surd}$HZ, the maximum sensitivity of -26.8 dBm for $10^{-12}BER$, and the power consumption of 27.6 mW from a single 1.8-V supply. The dual-channel chip occupies the area of $1.0{\times}0.73mm^2$ including I/O pads.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.691-692
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• 2016

본 논문은 802.11a 무선 랜용 5.25-GHz BiCMOS 저 잡음 증폭기를 제안한다. 이러한 회로는 1볼트 전원에서 동작하며, 저 전압 전원 공급에서도 높은 전압 이득을 가지도록 설계하였다. 제안한 회로는 $0.18{\mu}m$ SiGe HBT BiCMOS로 설계되어 있다. 저 전압 및 저 전력 동작을 위해 바이어스 회로는 밴드 갭 참조 (band-gap reference circuit) 바이어스 회로를 사용하였다. 제안한 회로는 최근 발표된 연구결과에 비해 높은 전압이득, 낮은 잡음지수 및 작은 칩 크기 특성을 보였다.

• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.1
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• pp.58-64
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• 2016

This study presents a design method for a single-loop voltage controller that is suitable for an arbitrary waveform generator (AWG). The voltage control algorithm of AWG should ensure high dynamic performance and should attain sufficient robustness to disturbances such as inverter nonlinearity, sensor noise, and load current. By analyzing the power circuit of AWG, control limitation and control target are presented to improve the dynamic performance of AWG. The proposed voltage control algorithm is composed of a single-loop output voltage control, an inverter current feedback term to improve transient response, and a load current feedforward term to prevent voltage distortion. The guideline for setting control gain is presented based on output filter parameters and digital time delay. The performance of the proposed algorithm is proven by experimental results through comparison with the conventional algorithm.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1260-1263
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• 2000

Vector control of a single phase induction machine(SPIM) is usually employed by mechanical methods than electrical ones. The disadvantage of a SPIM has large noise at the starting. Using auxiliary winding which is only utilized for starting, the SPIM can be controlled with the vector control method. Regarding a auxiliary winding one phase, the SPIM is analyzed by the unsymmetrical two phase motor and phase transformation is unnecessary such as three phase IM. Including a auxiliary winding, SPIM is modeled by mathematical getting by component of turns ratio with main to auxiliary winding. It will be take with complicated resultant formula, by comparison to symmetrical three phase TM. For using the vector control theory, it must be decoupled of rotor flux and torque component. stator current is controlled and decoupled. This paper presents a variable-speed control system of SPIM, which to decoupled with flux and torque component and to use machine equivalent circuit referred to rotor, conventionally three phase IM by similar method.