• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.2
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• pp.93-99
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• 2001

A new type geometric and mathematical network reduction model is introduced. Large-scale network is analyzed with analytic approach. The graph has many nodes, branches and loops. Circuit equation are obtained from these elements and connection rule. In this paper, the analytic relation between voltage source has a mutual different graphic property. Node-reduction procedure is achieved with this circuit property. Consequently voltage source value is included into the adjacent node-analyzing equation. A resultant model equations are reduced as much as voltage source number. Matrix rank is (n-1-k), where n, k is node and voltage source number. The reduction procedure is described and verified with geometric principle and circuit theory. Matrix type circuit equation can be composed with this technique. The last results shall be calculated by using computer.

• Proceedings of the KIPE Conference
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• 2015.11a
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• pp.9-10
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• 2015

EI core inductor in power electronic circuit simulation is usually assumed as linear by using matrix model. However, nonlinear magnetic characteristics such as B-H characteristic are also important for the accurate simulation of the circuit behavior. To model nonlinear magnetic characteristics of EI core inductor with only DC bias table, this paper presents a method in PLECS simulation tool which is a commercially available simulation tool for power electronics circuit analysis. Comparing with ideal matrix model, the simplification and accuracy are improved by this modeling method. Also, compared to analysis by FEM, it is much simpler, faster and easier to simulate with power electronics circuit. Validation of the proposed model was verified by simulation and experiment results.

• Journal of Practical Engineering Education
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• v.11 no.2
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• pp.143-150
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• 2019

Circuit theory is a systematic study that analyzes and designs the most basic circuits in the field of electrical and electronic engineering. Circuit theory courses are organized as major courses for one or two semesters in the second year of university, so that electrical and electronic engineering students must learn. Experimental courses are being together organized for students to enhance understanding of circuit theory and cultivate the skills and the abilities of circuit design through experiments with actual circuits. This paper is a case study on the teaching method applied in electric circuit design and experiment courses to enhance the learning effect on the experimental education that supports circuit theory. To do this, we propose a 15-week instructional model consisting of theory study, simulation, experiments, and design projects. In the proposed model, the simulation and preliminary experiment preparation process are reinforced to complement the theoretical concept and the design project is introduced to acquire practical circuit design skills as engineers. The results of five-year operation demonstrate the effectiveness of the proposed model.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.13-26
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• 1999

This paper presents a metric that can guide to optimal circuit models for interconnects among various models, given interconnect parameters and operating environment. To get this goal, we categorize interconnects into RC~c1ass and RLC-c1ass model domains based on the quantitative modeling error analysis using total resistance, inductance and capacitance of interconnects as well as operating frequency. RC~c1ass circuit models, which include most on~chip interconnects, can be efficiently analyzed by using the model~order reduction techniques. RLC-c1ass circuit models are constructed using one of three candidates, ILC(Iterative Ladder Circuit) macromodels, MC(Method of Characteristics) macromodels, and state-based convolution method, the selection process of which is based upon the allowable modeling error and electrical parameters of interconnects. We propose the model domain diagram leading to optimal circuit models and the division of model domains has been achieved considering the simulation cost of macromodels under the environmental assumption of the general purpose circuit simulator such as SPICE. The macromodeling method presented in this paper keeps the passivity of the original interconnects and accordingly guarantees the unconditional stability of circuit models.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.4
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• pp.10-16
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• 2021

This paper proposes a model that considers the parity-time symmetric structure as a state detection circuit for sensor applications using a stretchable inductor. In particular, to obtain a more practical computer simulation result, the stretchable inductor model was applied to this study model by referring to previously reported experimental results. The resistance component and phase component were controlled through the negative differential resistance circuit used in this study. In addition, the imbalance of the circuit caused by a change in the characteristics of the stretchable inductor could be compensated for using a negative differential resistance circuit. In particular, an analysis of the frequency characteristics of the sensor driving circuit of the parity-time symmetric structure proposed in this study confirmed that the Q-factor could be increased up to 20 times compared to the conventional resonant circuit.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.981-987
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• 1986

This paper describes the CIREX(CIRcuit EXtractor), an automated CMOS circuit extraction program which provides SPICE2 input file by computing circuit connectivity and transistor dimensions from the CIF file. The CIREX also computes parasitic capacitance and resistance which makes it a valuable tool for timing analysis and detailed circuit simulation. A lattice model is used to calculate the interconnection resistances and substrate capacitances which can be replaced, as an option, by a node model for the worst case timing analysis of the circuit.

• Journal of Sensor Science and Technology
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• v.15 no.1
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• pp.34-39
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• 2006

This study provides the electrical model of combustible catalytic gas sensor. Physical characteristics such as thermal behavior, resistance change were included in this model. The finite element method analysis for sensor device structure showed that the thermal behavior of sensor is expressed in a simple electrical equivalent circuit that consists of a resistor, a capacitor and a current source. This thermal equivalent circuit interfaces with real electrical circuit using two parts. One is 'power to heat' converter. The other is temperature dependent variable resistor. These parts realized with the analog behavior devices of the SPICE library. The gas response tendency was represented from the mass transferring limitation theory and the combustion theory. In this model, Gas concentration that is expressed in voltage at the model, is converted to heat and is flowed to the thermal equivalent circuit. This model is tested in several circuit simulations. The resistance change of device, the delay time due to thermal capacity, the gas responses output voltage that are calculated from SPICE simulations correspond well to real results from measuring in electrical circuits. Also good simulation result can be produced in the more complicated circuit that includes amplifier, bios circiut, buffer part.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.1119-1122
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• 2000

This paper describes on RF circuit simulation technique, especially on a RF modeling and a model extraction of a LDMOS(Lateral Diffused MOS) that has gate-width (Wg) dependence. Small-signal model parameters of the LDMOSs with various gate-widths extracted from S-parameter data are applied to make the relation between the RF performances and gate-width. It is proved that a source inductance (Ls) was not applicable to scaling rules. These extracted small-signal model parameters are also utilized to remove extrinsic elements in an extraction of a large-signal model (using HP Root MOSFET Model). Therefore, we can omit an additional measurement to extract extrinsic elements. When the large-signal model with Ls having the above gate-width dependence is applied to a high-power LDMOS module, the simulated performances (Output power, etc.) are in a good agreement with experimental results. It is proved that our extracted model and RF circuit simulation have a good accuracy.

• Journal of information and communication convergence engineering
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• v.19 no.4
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• pp.263-268
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• 2021

Although the compact capacitance model of point tunneling types of tunneling field-effect transistors (TFET) has been proposed, those of line tunneling types of TFETs have not been reported. In this study, a compact capacitance model of an L-shaped TFET (LTFET), a line tunneling type of TFET, is proposed using the previously developed surface potentials and current models of P- and L-type LTFETs. The Verilog-A LTFET model for simulation program with integrated circuit emphasis (SPICE) was also developed to verify the validation of the compact LTFET model including the capacitance model. The SPICE simulation results using the Verilog-A LTFET were compared to those obtained using a technology computer-aided-design (TCAD) device simulator. The current-voltage characteristics and capacitance-voltage characteristics of N and P-LTFETs were consistent for all operational bias. The voltage transfer characteristics and transient response of the inverter circuit comprising N and P-LTFETs in series were verified with the TCAD mixed-mode simulation results.

• Journal of the Korea Society of Computer and Information
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• v.1 no.1
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• pp.25-36
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• 1996

We have analyzed the reliability of failure models In grid topology circuit switched networks. These models are grid topology circuit_ switched networks. and each node transmits packets to object node using flooding search routing method. We hypothesized that the failure of each link Is Independent. We have analyzed for the performance estimation of failure models It using joint probability method to the reliability of a small grid topology circuit switched network. and compared analytic output with simulated output. Also. We have evaluated the reliability of networks using call blocking Probability occurred in circuit switched networks.