• 제목/요약/키워드: Circuit design

검색결과 5,391건 처리시간 0.033초

Sliding diagonal Pattern에 의한 Memory Test circuit 설계 (Design of Memory Test Circuit for Sliding Diagonal Patterns)

  • 김대환;설병수;김대용;유영갑
    • 전자공학회논문지A
    • /
    • 제30A권1호
    • /
    • pp.8-15
    • /
    • 1993
  • A concrete disign of memory circuit is presented aiming at the application of sliding diagonal test patterns. A modification of sliding diagonal test pattern includes the complexity reduction from O(n$^{32}$) to O(n) using parallel test memory concept. The control circuit design was based on delay-element, and verified via logic and circuit simulation. Area overhead was evaluated based on physical layout using a 0.7 micron design rule resulting in about 1% area increase for a typical 16Mbit DRAM.

  • PDF

$2^n$개의 노드를 갖는 DCG 특성에 대한 병렬3치 논리회로 설계에 관한 연구 (A Study on the Parallel Ternary Logic Circuit Design to DCG Property with 2n nodes)

  • 변기영;박승용;심재환;김흥수
    • 전자공학회논문지SC
    • /
    • 제37권6호
    • /
    • pp.42-49
    • /
    • 2000
  • 본 논문에서는 2ⁿ개의 노드를 갖는 DCG 특성에 대한 병렬 3치 논리회로를 설계하는 알고리즘을 제안하였다. 회로의 집적도를 높이기 위한 다양한 연구분야 중 전송선의 신호레벨을 증가시켜줌으로써 회로내의 배선밀도를 낮출 수 있으며 병렬신호전송을 통한 신호처리의 고속화, 회로의 특성을 만족시키며 최적화할 수 있는 회로설계알고리즘은 모두 고밀도 집적회로를 구현하기 위한 유용한 수단이 될 수 있다. 본 논문에서는 특히, 노드들의 개수가 2ⁿ개로 주어진 DCG에 대하여 그 특성을 행렬방정식으로 도출해내고 이를 통해 최적화 된 병렬3치 논리회로를 설계하는 과정을 정리하여 알고리즘으로 제안하였다. 또한, 설계된 회로의 동작특성을 만족하도록 DCG의 각 노드들의 코드를 할당하는 알고리즘도 제안하였다. 본 논문에서 제안된 알고리즘에 의해 회로결선의 감소와 처리속도 향상, 비용절감 측면에서 유용하다 할 수 있다.

  • PDF

Sub-threshold MOSFET을 이용한 전류모드 회로 설계 (Current-Mode Circuit Design using Sub-threshold MOSFET)

  • 조승일;여성대;이경량;김성권
    • 한국위성정보통신학회논문지
    • /
    • 제8권3호
    • /
    • pp.10-14
    • /
    • 2013
  • 본 논문에서는 저전력 기술인 DVFS (Dynamic Voltage Frequency Scaling) 응용을 위하여, 동작주파수의 변화에도 소비전력이 일정한 특성을 갖는 전류모드 회로를 적용함에 있어서, 저속 동작에서 소비전력이 과다한 전류모드 회로의 문제점을 전류모드 회로에서 sub-threshold 영역 동작의 MOSFET을 적용함으로써 소비전력을 최소화하는 설계기술을 소개한다. 회로설계는 MOSFET BSIM 3모델을 사용하였으며, 시뮬레이션한 결과, strong-inversion 동작일 때 소비전력은 $900{\mu}W$이었으나, sub-threshold 영역으로 동작하였을 때, 소비전력이 $18.98{\mu}W$가 되어, 98 %의 소비전력의 절감효과가 있음을 확인하였다.

유한 요소 해석을 통한 자기변형 구동기 자기 회로 설계 (The design of magnetic circuit of magnetostrictive actuator using finite element method)

  • 이석호;박영우
    • 한국정밀공학회:학술대회논문집
    • /
    • 한국정밀공학회 2004년도 추계학술대회 논문집
    • /
    • pp.548-551
    • /
    • 2004
  • Magnetostrictive actuators have seen increasing use in fine positioning system because it has many advantages such as friction free, resolution of ${\mu}{\textrm}{m}$ or nm scale, and powerful output force. Usually, the magnetic circuit of magnetostrictive actuator has components which are flux return path, coil, and magnetostrictive material. It is classified in two types according to existence of the permanent magnet. The magnetic circuit having optimal performances transfer magnetic field which is obtained by providing input current at coil without energy loss. This paper described mathematical model of magnetic circuit for getting design variables. The modeling equation is obtained from the relations between flux and reluctance of the magnetic equivalent circuit. Also, finite element analysis has been used to study the performance of magnetic circuit according to change of design variables such as existence and shape of the permanent magnet, flux return path etc. The modification of dimensions enables us to optimize magnetic circuit.

  • PDF

DTG의 性質을 갖는 高速竝列多値論理回路의 設計에 관한 硏究 (A Study on the Highly Parallel Multiple-Valued Logic Circuit Design with DTG Properties)

  • 나기수;신부식;최재석;박춘명;김흥수
    • 전자공학회논문지C
    • /
    • 제36C권6호
    • /
    • pp.27-36
    • /
    • 1999
  • 본 논문에서는 입출력간의 연관관계가 트리구조로 표현되는 DTG에 의한 고속병렬다치논리회로를 설계하는 알고리즘을 제안하였다. 본 논문에서는 Nakajima 등에 의해 제안된 알고리즘의 문제점을 도출한 후, 최적화된 분할연산회로설계를 위하여 트리구조에 기초를 둔 수학적인 해석의 개념을 소개한다. 본 논문에서 제안한 알고리즘은 Nakajima 등에 의해 제안된 알고리즘으로는 설계가 가능하지 않았던 임의의 절점을 갖는 DTG에 대해서도 회로를 설계할 수 있다는 장점이 있다. Nakajima 등에 의해 제안된 알고리즘과 본 논문에서 제한한 알고리즘을 회로설계의 관점에서 비교하여 본 논문의 알고리즘이 모든 경우의 DTG에서 보다 최적화 설계를 할 수 있음을 증명하였다. 그리고 예제를 통해 본 논문에서 제안한 알고리즘의 유용성을 증명해 보였다.

  • PDF

Optimization of the Spring Design Parameters of a Circuit Breaker to Satisfy the Specified Dynamic Characteristics

  • Gil Young;Kwang Young
    • International Journal of Precision Engineering and Manufacturing
    • /
    • 제5권4호
    • /
    • pp.43-49
    • /
    • 2004
  • A spring-actuated linkage system is used to satisfy the desired opening and closing characteristics of the electric contacts of a vacuum circuit breaker. If the type of a circuit breaker and the structure of the linkage system are predetermined, then design parameters such as stiffness, free length and attachment points of the spring become the important issues. In this paper, based on the energy conservation, the total system energy is constant throughout the operating range of the mechanism; a systematic procedure to optimize the spring design parameters is developed and applied to a simplified mechanism of a circuit breaker. The developed procedure is converted to the environment of the multi-body dynamics program, ADAMS for an in-depth consideration of the complex dynamics of a circuit breaker mechanism.

규정된 동적특성을 위한 회로차단기의 스프링 설계변수의 최적화 (Optimization of the Spring Design Parameters of a Circuit Breaker for Satisfying Specified Dynamic Characteristics)

  • 안길영;정광영
    • 한국정밀공학회지
    • /
    • 제21권3호
    • /
    • pp.132-138
    • /
    • 2004
  • In a vacuum circuit breaker mechanism, a spring-actuated linkage system is used to satisfy the desired opening and closing characteristics of electric contacts. If the type and structure of the linkage system required to the circuit breaker is predetermined, the stiffness, free length and attachment points of a spring become the important design parameters. In this paper, based on the energy conservation that the total system energy is constant throughout the operating range of the mechanism, a systematic procedure for optimizing the spring design parameters is developed and applied to the simplified mechanism of a circuit breaker. Then, in order to consider the complex dynamics of the circuit breaker mechanism rather well, the developed procedure is converted to the environment of a multi-body dynamics program ADAMS.

저가의 단 문장 음성 인식회로 설계 (Low Cost Circuit Design for a Sentence Speech Recognition)

  • 최지혁;홍광석
    • 대한전자공학회:학술대회논문집
    • /
    • 대한전자공학회 2002년도 하계종합학술대회 논문집(4)
    • /
    • pp.365-368
    • /
    • 2002
  • In this paper, we present a low cost circuit design for a sentence speech recognition. The basic circuit of the designed sentence speech recognizer is composed of resistor, capacitance, OP Amp, counter and logic gates. Through a sentence recognition experiment, we can find the effectiveness of the designed sentence recognition circuit

  • PDF

레이저를 이용한 거리센서의 디지털 회로의 설계 (A Design of Digital Laser Theodolite)

  • 최인원;김현철;유수엽;윤희상
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 2006년도 심포지엄 논문집 정보 및 제어부문
    • /
    • pp.330-332
    • /
    • 2006
  • A short distance laser range detector was developed on digital circuit. The circuit changed the analog circuit to digital circuit as possible as. The currently available laser range circuit one uses analog circuit mainly. But this ranger design targeted mass production with digital reporting function. So digital circuits replaced the analog circuit except amplifier and remained minor circuits those are hard to replace with digital circuit. The simulation shows that it is possible to make a reasonable distance measuring circuit on a digital circuit for very low price compare to analog circuit one.

  • PDF

A 32-Gb/s Inductorless Output Buffer Circuit with Adjustable Pre-emphasis in 65-nm CMOS

  • Tanaka, Tomoki;Kishine, Keiji;Tsuchiya, Akira;Inaba, Hiromi;Omoto, Daichi
    • IEIE Transactions on Smart Processing and Computing
    • /
    • 제5권3호
    • /
    • pp.207-214
    • /
    • 2016
  • Optical communication systems are rapidly spread following increases in data traffic. In this work, a 32-Gb/s inductorless output buffer circuit with adjustable pre-emphasis is proposed. The proposed circuit consists of an output buffer circuit and an emphasis circuit. The emphasis circuit emphasizes the high frequency components and adds the characteristics of the output buffer circuit. We proposed a design method using a small-signal equivalent-circuit model and designed the compensation characteristics with a 65-nm CMOS process in detail using HSPICE simulation. We also realized adjustable emphasis characteristics by controlling the voltage. To confirm the advantages of the proposed circuit and the design method, we fabricated an output buffer IC with adjustable pre-emphasis. We measured the jitter and eye height with a 32-Gb/s input using the IC. Measurement results of double-emphasis showed that the jitter was 14% lower, and the eye height was 59% larger than single-emphasis, indicating that our proposed configuration can be applied to the design of an output buffer circuit for higher operation speed.