• Title/Summary/Keyword: Circuit Emulator

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Practical Implementation of Memristor Emulator Circuit on Printed Circuit Board (PCB에 구현한 멤리스터 에뮬레이터 회로 및 응용)

  • Choi, Jun-Myung;Sin, SangHak;Min, Kyeong-Sik
    • Journal of IKEEE
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    • v.17 no.3
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    • pp.324-331
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    • 2013
  • In this paper, we implemented memristor emulator circuit on Printed Circuit Board (PCB) and observed the inherent pinched hysteresis characteristic of memristors by measuring the emulator circuit on PCB. The memristor emulator circuit implemented on PCB is composed of simple discrete devices not using any complicated circuit blocks thus we can integrate the memristor emulator circuits in very small layout area on Silicon substrate. The programmable gain amplifier is designed using the proposed memristor emulator circuit and verified that the amplifier's voltage gain can be controlled by programming memristance of the emulator circuit by circuit simulation. Threshold switching is also realized in the proposed emulator circuit thus memristance can remain unchanged when the input voltage applied to the emulator circuit is lower than VREF. The memristor emulator circuit and the programmable gain amplifier using the proposed circuit can be useful in teaching the device operation, functions, characteristics, and applications of memristors to students when thet cannot access to device and fabrication technologies of real memristors.

Floating Memristor Emulator Circuit (비접지형 멤리스터 에뮬레이터 회로)

  • Kim, Yongjin;Yang, Changju;Kim, Hyongsuk
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.8
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    • pp.49-58
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    • 2015
  • A floating type of memristor emulator which acts like the behavior of $TiO_2$ memristor has been developed. Most of existing memristor emulators are grounded type which is built disregarding the connectivity with other memristor or other devices. The developed memristor emulator is a floating type whose output does not need to be grounded. Therefore, the emulator is able to be connected with other devices and be utilized for the interoperability test with various other circuits. To prove the floating function of the proposed memristor emulator, a Wheatstone bridge is built by connecting 4 memristor emulators in series and parallel. Also this bridge circuit suggest that it is possible to weight calculation of the neural network synapse.

Comparative Analysis of Synthetic Memristor Emulator and M-R Mutator (합성형 멤리스터 에뮬레이터와 M-R 뮤테이터의 특성 비교)

  • Choi, Hyuncheol;Kim, Hyongsuk
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.5
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    • pp.98-107
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    • 2016
  • An analytical comparison of a synthetic memristor emulator and a M-R mutator-based memristor emulator has been performed. Memristor is an electrical element with the characteristic of variable resistance. It is called the fourth fundamental electrical element following resistor, capacitor, and inductor. Memristor emulator is a circuit which implements the feature of variable resistance via the composition of various electrical devices. It is an essential circuit to study memristor characteristics during the time before it is commercially available. There are two representative memristor emulators depending upon their implementation methods. One is a memristor emulator which is synthesized via combining various electrical devices and the other one is M-R mutator-based memristor emulator implemented by extracting resistance from a nonlinear device. In this paper, implementation methods of these two memristor emulators are studied and their differences are investigated by analysing their characteristics.

Experimental Assessment with Wind Turbine Emulator of Variable-Speed Wind Power Generation System using Boost Chopper Circuit of Permanent Magnet Synchronous Generator

  • Tammaruckwattana, Sirichai;Ohyama, Kazuhiro;Yue, Chenxin
    • Journal of Power Electronics
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    • v.15 no.1
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    • pp.246-255
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    • 2015
  • This paper presents experimental results and its assessment of a variable-speed wind power generation system (VSWPGS) using permanent magnet synchronous generator (PMSG) and boost chopper circuit (BCC). Experimental results are obtained by a test bench with a wind turbine emulator (WTE). WTE reproduces the behaviors of a windmill by using servo motor drives. The mechanical torque references to drive the servo motor are calculated from the windmill wing profile, wind velocity, and windmill rotational speed. VSWPGS using PMSG and BCC has three speed control modes for the level of wind velocity to control the rotational speed of the wind turbine. The control mode for low wind velocity regulates an armature current of generator with BCC. The control mode for middle wind velocity regulates a DC link voltage with a vector-controlled inverter. The control mode for high wind velocity regulates a pitch angle of the wind turbine with a pitch angle control system. The hybrid of three control modes extends the variable-speed range. BCC simplifies the maintenance of VSWPGS while improving reliability. In addition, VSWPGS using PMSG and BCC saves cost compared with VSWPGS using a PWM converter.

Emulator Circuit for a Flux Locked Loop for Detection of Magnetocardiography Signal (심자도 신호 검출을 위한 Flux Locked Loop (FLL) Emulation 회로)

  • 안창범;이동훈;김인기;장경섭;김기태;정동현;최중필
    • Proceedings of the IEEK Conference
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    • 2003.07c
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    • pp.2749-2752
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    • 2003
  • Magnetocardiography is a very weak biomagnetic field generated from the heart. Since the magnitude of the biomagnetic field is in the order of a few pico Tesla, it is measured with a superconducting quantum interference device (SQUID). SQUID is a transducer converting magnetic flux to voltage, however, its range of linear conversion is very restricted. In order to overcome the narrow dynamic range. a flux locked loop is used to feedback the output field with opposite polarity to the input field so that the total Held becomes zero. This prevents the operating point of the SQUID from moving too far away from the null point thereby escape from the linear region. In this paper, an emulator for the SQUID sensor and feedback coil is proposed. Magnetic courting between the original field and the generated field by the feedback coil is emulated by electronic circuits. By using the emulator, FLL circuits are analyzed and optimized without SQUID sensors. The emulator may be used as a test signal for multi-channel gain calibration and system maintenance.

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Sensing of Three Phase PWM Voltages Using Analog Circuits (아날로그 회로를 이용한 3상 PWM 출력 전압 측정)

  • Jou, Sung-Tak;Lee, Kyo-Beum
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.64 no.11
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    • pp.1564-1570
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    • 2015
  • This paper intends to suggest a sensing circuit of PWM voltage for a motor emulator operated in the inverter. In the emulation of the motor using a power converter, it is necessary to measure instantaneous voltage at the PWM voltage loaded from the inverter. Using a filter can generate instantaneous voltage, while it is difficult to follow the rapidly changing inverter voltage caused by the propagation delay and signal attenuation. The method of measuring the duty of PWM using FPGA can generate output voltage from the one-cycle delay of PWM, while the cost of hardware is increasing in order to acquire high precision. This paper suggests a PWM voltage sensing circuit using the analogue system that shows high precision, one-cycle delay of PWM and low-cost hardware. The PWM voltage sensing circuit works in the process of integrating input voltage for valid time by comparing levels of three-phase PWM input voltage, and produce the output value integrated at zero vector. As a result of PSIM simulation and the experiment with the produced hardware, it was verified that the suggested circuit in this paper is valid.

SCATOMi : Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture

  • Young-Su kwon;Kyung, Chong-Min
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.823-826
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    • 2003
  • FPGA-based logic emulator with lane gate capacity generally comprises a large number of FPGAs connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multi-FPGA system incorporating several state-of-the-art FPGAs. This paper proposes a circuit partitioning algorithm called SCATOMi(SCheduling driven Algorithm for TOMi)for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi(Time-multiplexed, Off-chip, Multicasting interconnection). SCATOMi improves the performance of TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Architecture comparison show that the pin count is reduced to 15.2%-81.3% while the critical path delay is reduced to 46.1%-67.6% compared to traditional architectures.

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A Study on the ISDN Telephone User-Network Interface -Part 1: A Study on the Implementation of A Circuit Switching Emulator for ISDN- (ISDN용 전화가입자 - 망 간 접속에 관한 연구 -제 1 부 : ISDN용 회선 교환 Emulator구성에 관한 연구-)

  • 박영덕;장진상;김영철;조규섭;박병철
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.12 no.1
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    • pp.60-70
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    • 1987
  • Recently the tendency of the network system development rapidly progresses toward ISDN that intergrates all presetn-day communication networks and services into a single, universal network set up on the basis of the exisiting telephone network. For this reason many countries pay worldwide attention to the researches about ISDN, especially to the researches about the exchange and the ISDN user-network interface which is one of the most important parts of network system. This paper is the first part of the two-par papers describing the ISDN user-network interface. in this paper, after surveying the architecture of ISDN exchange recommended by CCITT, the general architecture of the ISDN exchage is proposed, Based on this architecture, the switching emulator is implemented, and the necessary conditions of the ISDN exchage(LAPO, CCP etc) are also studied.

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REGO: REconfiGurable system emulatOr (레고 : 재구성 가능한 시스템 에뮬레이터)

  • Kim, Nam-Do;Yang, Se-Yang
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.2
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    • pp.91-103
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    • 2002
  • For massive FPGA based emulator, the interconnection architecture and the transmission method of signals between FPGA's are important elements which decide speed of emulation and extendability of emulator. Existing FPGA-based emulation system is faced the problems of which the emulation speed getting slow drastically as the complexity of circuit increases. In this paper, we proposed a new innovative emulation architecture that has high resource usage rate and makes the fast emulation Possible. The emulator with very unique hierarchical ring topology Presented here has merits to overcome FPGA pin limitation by connecting each FPGA into a set of pipelined rings, and it also makes emulation speed at the tens of MHz at least even at system level where the verification complexity can easily exceed the verification capability of designers.

Development of Circuit Emulator Solution using Raspberry Pi System (라즈베리파이 시스템을 이용한 회로 에뮬레이터 솔루션 개발)

  • Nah, Bang-hyun;Lee, Young-woon;Kim, Byung-gyu
    • Journal of Digital Contents Society
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    • v.18 no.3
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    • pp.607-612
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    • 2017
  • The use of RaspberryPi in building an embedded system may be difficult for users in understanding the circuit and the hardware cost. This paper proposes a solution that can test the systems virtually. The solution consists of three elements; (i) editor, (ii) interpreter and (iii) simulator and provides nine full modules and also allows the users to configure/run/test their own circuits like real environment. The task of abstraction for modules through the actual circuit test was carried out on the basis of the data sheet and the specification provided by the manufacturer. If we can improve the level of quality of our solution, it can be useful in terms of cost reduction and easy learning. To achieve this end, the electrical physics engine, the level of interpreter that can be ported to the actual board, and a generalization of the simulation logic are required.