• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.1
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• pp.8-15
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• 1993

A concrete disign of memory circuit is presented aiming at the application of sliding diagonal test patterns. A modification of sliding diagonal test pattern includes the complexity reduction from O(n$^{32}$) to O(n) using parallel test memory concept. The control circuit design was based on delay-element, and verified via logic and circuit simulation. Area overhead was evaluated based on physical layout using a 0.7 micron design rule resulting in about 1% area increase for a typical 16Mbit DRAM.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.42-49
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• 2000

In this paper, we propose the parallel ternary logic circuit design algorithm to DCG Property with 2$^n$ nodes. To increase circuit integration, one of the promising approaches is the use of multiple-valued logic(MVL). It can be useful methods for the realization of compact integrated circuit, the improvement of high velocity signal processing using parallel signal transmission and the circuit design algorithm to optimize and satisfy the circuit property. It is all useful method to implement high density integrated circuit. In this paper, we introduce matrix equation to satisfy given DCG with 2$^n$ nodes, and propose the parallel ternary logic circuit design process to circuit design algorithm. Also, we propose code assignment algorithm to satisfy for the given DCG property. According to the simulation result of proposed circuit design algorithm, it have the following advantage ； reduction of the circuit signal lines, computation time and costs.

• Journal of Satellite, Information and Communications
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• v.8 no.3
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• pp.10-14
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• 2013

In this paper, when applying current-mode circuit design technique showing constant power dissipation none the less operation frequency, to the low power design of dynamic voltage frequency scaling, we introduce the low power current-mode circuit design technique applying MOSFET in sub-threshold region, in order to solve the problem that has large power dissipation especially on the condition of low operating frequency. BSIM 3, was used as a MOSFET model in circuit simulation. From the simulation result, the power dissipation of the current memory circuit with sub-threshold MOSFET showed $18.98{\mu}W$, which means the consumption reduction effect of 98%, compared with $900{\mu}W$ in that with strong inversion. It is confirmed that the proposed circuit design technique will be available in DVFS using a current-mode circuit design.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.548-551
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• 2004

Magnetostrictive actuators have seen increasing use in fine positioning system because it has many advantages such as friction free, resolution of ${\mu}{\textrm}{m}$ or nm scale, and powerful output force. Usually, the magnetic circuit of magnetostrictive actuator has components which are flux return path, coil, and magnetostrictive material. It is classified in two types according to existence of the permanent magnet. The magnetic circuit having optimal performances transfer magnetic field which is obtained by providing input current at coil without energy loss. This paper described mathematical model of magnetic circuit for getting design variables. The modeling equation is obtained from the relations between flux and reluctance of the magnetic equivalent circuit. Also, finite element analysis has been used to study the performance of magnetic circuit according to change of design variables such as existence and shape of the permanent magnet, flux return path etc. The modification of dimensions enables us to optimize magnetic circuit.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.27-36
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• 1999

This paper proposes algorithms that design the highly parallel multiple-valued logic circuit of DTG(Directed Tree Graph) to be represented by tree structure relationship between input and output of nodes. The conventional Nakajima's algorithms have some problems so that this paper introduce the concept of mathematical analysis based on tree structure to design optimized locally computable circuit. Using the proposed circuit design algorithms in this paper it is possible to design circuit in that DTG have any node number - not to design by Nakajima's algorithms. Also, making a comparison between the circuit design using Nakajim's algorithms and this paper's, we testify that proposed algorithms in this paper optimizes circuit design all case of DTG. Some examples are shown to demonstrate the usefulness of the circuit design algorithm.

• International Journal of Precision Engineering and Manufacturing
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• v.5 no.4
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• pp.43-49
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• 2004

A spring-actuated linkage system is used to satisfy the desired opening and closing characteristics of the electric contacts of a vacuum circuit breaker. If the type of a circuit breaker and the structure of the linkage system are predetermined, then design parameters such as stiffness, free length and attachment points of the spring become the important issues. In this paper, based on the energy conservation, the total system energy is constant throughout the operating range of the mechanism; a systematic procedure to optimize the spring design parameters is developed and applied to a simplified mechanism of a circuit breaker. The developed procedure is converted to the environment of the multi-body dynamics program, ADAMS for an in-depth consideration of the complex dynamics of a circuit breaker mechanism.

• Journal of the Korean Society for Precision Engineering
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• v.21 no.3
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• pp.132-138
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• 2004

In a vacuum circuit breaker mechanism, a spring-actuated linkage system is used to satisfy the desired opening and closing characteristics of electric contacts. If the type and structure of the linkage system required to the circuit breaker is predetermined, the stiffness, free length and attachment points of a spring become the important design parameters. In this paper, based on the energy conservation that the total system energy is constant throughout the operating range of the mechanism, a systematic procedure for optimizing the spring design parameters is developed and applied to the simplified mechanism of a circuit breaker. Then, in order to consider the complex dynamics of the circuit breaker mechanism rather well, the developed procedure is converted to the environment of a multi-body dynamics program ADAMS.

• Proceedings of the IEEK Conference
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• 2002.06d
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• pp.365-368
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• 2002

In this paper, we present a low cost circuit design for a sentence speech recognition. The basic circuit of the designed sentence speech recognizer is composed of resistor, capacitance, OP Amp, counter and logic gates. Through a sentence recognition experiment, we can find the effectiveness of the designed sentence recognition circuit

• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.330-332
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• 2006

A short distance laser range detector was developed on digital circuit. The circuit changed the analog circuit to digital circuit as possible as. The currently available laser range circuit one uses analog circuit mainly. But this ranger design targeted mass production with digital reporting function. So digital circuits replaced the analog circuit except amplifier and remained minor circuits those are hard to replace with digital circuit. The simulation shows that it is possible to make a reasonable distance measuring circuit on a digital circuit for very low price compare to analog circuit one.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.3
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• pp.207-214
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• 2016

Optical communication systems are rapidly spread following increases in data traffic. In this work, a 32-Gb/s inductorless output buffer circuit with adjustable pre-emphasis is proposed. The proposed circuit consists of an output buffer circuit and an emphasis circuit. The emphasis circuit emphasizes the high frequency components and adds the characteristics of the output buffer circuit. We proposed a design method using a small-signal equivalent-circuit model and designed the compensation characteristics with a 65-nm CMOS process in detail using HSPICE simulation. We also realized adjustable emphasis characteristics by controlling the voltage. To confirm the advantages of the proposed circuit and the design method, we fabricated an output buffer IC with adjustable pre-emphasis. We measured the jitter and eye height with a 32-Gb/s input using the IC. Measurement results of double-emphasis showed that the jitter was 14% lower, and the eye height was 59% larger than single-emphasis, indicating that our proposed configuration can be applied to the design of an output buffer circuit for higher operation speed.