• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.7
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• pp.1639-1645
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• 2015

In UHD high-speed video transmission system, when a signal within certain frequency region coincides electrically and structurally, the system becomes unstable because the energy is concentrated, and signal flux is interfered and distorted. For the instability, power integrity analysis should be conducted. To remove the signal distortion for MLB, using a high-frequency design technique for EMI phenomenon, EMI which radiates electromagnetic energy fluxed into power layer was analyzed considering system stabilization. In this paper, we proposed an adaptive MLB design method which minimizes high-frequency noise in MLB structure, enhances signal integrity and power integrity, and suppresses EMI. The characteristic impedance for multi-layer circuit board proposed in this study were High-Speed Video Differential Signaling(HSVDS) line width w = 0.203, line gap d = 0.203, beta layer height h = 0.145, line thickness t = 0.0175, dielectric constant ε_r = 4.3, and characteristic impedance Zdiff = 100.186Ω. When high-speed video differential signal interface board was tested with optimized parameters, the magnitude of Eye diagram output was 672mV, jittering was 6.593ps, transmission frequency was 1.322GHz, signal to noise was 29.62dB showing transmission quality improvement of 10dB compared to previous system.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.6
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• pp.619-628
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• 2019

In this paper, we designed a beta ray sensor for a true random number generator. Instead of biasing the gate of the PMOS feedback transistor to a DC voltage, the current flowing through the PMOS feedback transistor is mirrored through a current bias circuit designed to be insensitive to PVT fluctuations, thereby minimizing fluctuations in the signal voltage of the CSA. In addition, by using the constant current supplied by the BGR (Bandgap Reference) circuit, the signal voltage is charged to the VCOM voltage level, thereby reducing the change in charge time to enable high-speed sensing. The beta ray sensor designed with 0.18㎛ CMOS process shows that the minimum signal voltage and maximum signal voltage of the CSA circuit which are resulted from corner simulation are 205mV and 303mV, respectively. and the minimum and maximum widths of the pulses generated by comparing the output signal through the pulse shaper with the threshold voltage (VTHR) voltage of the comparator, were 0.592㎲ and 1.247㎲, respectively. resulting in high-speed detection of 100kHz. Thus, it is designed to count up to 100 kilo pulses per second.

• Journal of IKEEE
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• v.14 no.2
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• pp.51-57
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• 2010

A CMOS rail-to-rail high voltage buffer amplifier is proposed to drive the gamma correction reference voltage of large TFT LCD panels. It is operating by a single supply and only shows current consumption of 0.5mA at 18V power supply voltage. The circuit is designed to drive the gamma correction voltage of 8-bit or 10-bit high resolution TFT LCD panels. The buffer has high slew rate, 0.5mA static current and 1k$\Omega$ resistive and capacitive load driving capability. Also, it offers wide supply range, offset voltages below 50mV at 5mA constant output current, and below 2.5mV input referred offset voltage. To achieve wide-swing input and output dynamic range, current mirrored n-channel differential amplifier, p-channel differential amplifier, a class-AB push-pull output stage and a input level detector using hysteresis comparator are applied. The proposed circuit is realized in a high voltage 0.18um 18V CMOS process technology for display driver IC. The circuit operates at supply voltages from 8V to 18V.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.11
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• pp.695-700
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• 2018

This paper presents the development of compact and lightweight broadband power amplifier module using HMIC (Hybrid Microwave Integrated Circuit) technology that could be high-density integration for many non-packaged microwave components into the small area of a high dielectric constant printed circuit board, such as a ceramic substrate, also using the special design and fabrication schemes for the structure of minimized electromagnetic interference to obtain the homogeneous electrical performance at the wideband frequency. The results confirmed that the small signal gain has a gain flatness of ${\pm}1.5dB$ within the range of 32 to 36 dB. In addition, the output power satisfied more than 30 dBm. The noise figure was measured within 7 dB, and OIP3 (Output Third Order Intercept Point) was more than 39 dBm. The fabricated broadband power amplifier satisfied the target specification required to electrically drive the high power amplifiers of jamming generators for electronic warfare, so the actual applicability to the system was verified. Future studies will be aimed at designing other similar microwave power amplifiers in the future.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.2
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• pp.302-312
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• 2012

In this paper, small-area and high-reliability design techniques of a 512-bit EEPROM are designed for UHF RFID tag chips. For a small-area technique, there are a WL driver circuit simplifying its decoding logic and a VREF generator using a resistor divider instead of a BGR. The layout size of the designed 512-bit EEPROM IP with MagnaChip's $0.18{\mu}m$ EEPROM is $59.465{\mu}m{\times}366.76{\mu}m$ which is 16.7% smaller than the conventional counterpart. Also, we solve a problem of breaking 5V devices by keeping VDDP voltage constant since a boosted output from a DC-DC converter is made discharge to the common ground VSS instead of VDDP (=3.15V) in getting out of the write mode.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.319-319
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• 2013

Even though the fabrication methods of metal oxide based thin film capacitor have been well established such as RF sputtering, Sol-gel, metal organic chemical vapor deposition (MOCVD), ion beam assisted deposition (IBAD) and pulsed laser deposition (PLD), an applicable capacitor of printed circuit board (PCB) has not realized yet by these methods. Barium Strontium Titanate (BST) and other high-k ceramic oxides are important materials used in integrated passive devices, multi-chip modules (MCM), high-density interconnect, and chip-scale packaging. Thin film multi-layer technology is strongly demanded for having high capacitance (120 nF/$mm^2$). In this study, we suggest novel multi-layer thin film capacitor design and fabrication technology utilized by plasma assisted deposition and photolithography processes. Ba0.6Sr0.4TiO3 (BST) was used for the dielectric material since it has high dielectric constant and low dielectric loss. 5-layered BST and Pt thin films with multi-layer sandwich structures were formed on Pt/Ti/$SiO_2$/Si substrate by RF-magnetron sputtering and DC-sputtering. Pt electrodes and BST layers were patterned to reveal internal electrodes by photolithography. SiO2 passivation layer was deposited by plasma-enhanced chemical vapor deposition (PE-CVD). The passivation layer plays an important role to prevent short connection between the electrodes. It was patterned to create holes for the connection between internal electrodes and external electrodes by reactive-ion etching (RIE). External contact pads were formed by Pt electrodes. The microstructure and dielectric characteristics of the capacitors were investigated by scanning electron microscopy (SEM) and impedance analyzer, respectively. In conclusion, the 0402 sized thin film multi-layer capacitors have been demonstrated, which have capacitance of 10 nF. They are expected to be used for decoupling purpose and have been fabricated with high yield.

• Journal of Advanced Navigation Technology
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• v.12 no.2
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• pp.122-131
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• 2008

In this paper, an S-band oscillator of the low phase noise property using miniaturized microstrip hairpin shaped ring resonator has been designed and implemented. The TACONIC's RF-35 substrate has a dielectric constant ${\varepsilon}_r$=3.5 a thickness h=20mil a copper thickness t=17 um and loss tangent $tan{\delta}$=0.0025. The designed and implemented 2.45 GHz oscillator shows low phase performance of -100.5 dBc/Hz a 100kHz offset. Output power 20.9 dBm at center frequency 2.45 GHz and harmonic suppression -32 dBc. The circuit was implemented with hybrid technique. But can be fully compatible with the RFIC's, MIC and MMIC due to its entirely planar structure.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.1
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• pp.115-119
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• 2008

In this paper, the linearity of Doherty power amplifier has been improved by applying a new Photonic Bandgap(PBG) structure on the output of amplifier. The reposed spiral PBG structure is a two-dimensional(2-D) periodic lattice patterned on a dielectric slab that does not require nonplanar fabrication process. This structure has more broad stopband and high suppression performance than the conventional three cell PBG. Also, It has a sharp skirt property. We obtained the 3rd-order intermodulation distortion(IMD3) of -33dBc for CDMA applications with that of maintaining the constant power added efficiency(PAE), the IMD3 performance is improved as much as -8 dB compared with a Doherty power amplifier without PBG structure. Moreover, the physical length of PBG is shortened, therefore the whole amplifier circuit size is considerably reduced.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.4
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• pp.357-365
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• 2013

The 4 by 4 series slot sub-array antenna is proposed using substrate integrated waveguide(SIW) technology for 35 GHz of Ka band application. The proposed antenna is realized with multi-layered structure for compact size and easy integration features. 4 by 4 radiating slots are arrayed on top PCB with equal spacing and the feeding SIWs are arranged on middle and bottom PCBs for uniform power distribution. The multi-layered antenna is realized using RT/Duroid 5880 that has dielectric constant of 2.2 and the total antenna size is $750.76mm^2$. The individual parts such as radiators and feeding networks are simulated using full-wave simulator CST MWS. Furthermore, the total sub-array antenna also fabricated and measured the electrical performances such as impedance bandwidth under the criteria of -10 dB(490 MHz), maximum gain(18.02 dBi), sidelobe level(SLL)(-11.0 dB), and cross polarization discrimination (XPD)(-20.16 dB).

• Composites Research
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• v.31 no.5
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• pp.238-245
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• 2018

The hydrodynamic ram (HRAM) phenomenon is one of the main types of ballistic battle damages of a military aircraft and has great importance to airframe survivability design. The HRAM effect occurs due to the interaction between the fluid and structure, and damage can be investigated by measuring the pressure of the fluid and the dynamic strains on the structure. In this paper, HRAM test of a composite T-Joint was performed using a ram simulator which can generate HRAM pressure. In addition, calibration tests of PVDF sensor were performed to determine the circuit capacitance and time constant of the measurement system. The failure behavior of the composite T-Joint due to HRAM pressure was examined using the strain gauges and a PVDF sensor which were attached to the surface of the composite T-Joint.