• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.17 no.10
• /
• pp.1109-1116
• /
• 1992

Mathematical morphology, theoretical foundation for morphological filter, is very efficient for the analysis of the geometrical characteristics of signals and systems and is used as a predominant tool for smoothing the data with noise. In this study, H/W design of morphological filter is implemented to process the gray scale dilation and the erosion in the same circuit and to choose the maximum and minimum value by a selector, resulting in their education of the complexity of the circuit and an architecture for parallel processing. The structure of morphological filter consists of the structuring-element block, the image data block, the control block, the ADD block, the MIN/MAX block, etc, and is designed on an one-chip for real time operation.

• KIEE International Transactions on Power Engineering
• /
• v.3A no.2
• /
• pp.79-84
• /
• 2003

Unbalanced systems, such as distribution systems, have difficulties in fault locations due to single-phase laterals and loads. This paper proposes new fault locations developed by the direct three-phase circuit analysis algorithms using matrix inverse lemma for the line-to-ground fault case and the line-to-line fault case in unbalanced systems. The fault location for balanced systems has been studied using the current distribution factor, by a conventional symmetrical transformation, but that for unbalanced systems has not been investigated due to their high complexity. The proposed algorithms overcome the limit of the conventional algorithm using the conventional symmetrical transformation, which requires the balanced system and are applicable to any power system but are particularly useful for unbalanced distribution systems. Their effectiveness has been proven through many EMTP simulations.

• Journal of Power Electronics
• /
• v.19 no.1
• /
• pp.1-10
• /
• 2019

Current imbalance is the main factor affecting the lifespan of light-emitting diode (LED) lighting systems and is generally solved by active or passive approaches. Given many new lighting applications, independent control is particularly important in achieving different levels of luminance. Existing passive and active approaches have their own limitations in current sharing and independent control, which bring new challenges to the design of LED drivers. In this work, a multichannel resonant converter based on switched-capacitor control (SCC) is proposed for solving this challenge. In the resonant network of the upper and lower half-bridges, SCC is used instead of fixed capacitance. Then, the individual current of the LED array is obtained through regulation of the effective capacitance of the SCC under a fixed switching frequency. In this manner, the complexity of the control unit of the circuit and the precision of the multichannel outputs are further improved. Finally, the superior performance of the proposed LED driver is verified by simulations and a 4-channel experimental prototype with a rated output power of 20 W.

• Progress in Superconductivity
• /
• v.3 no.1
• /
• pp.17-22
• /
• 2001

Practical implementation of the SFQ technology in most application requires more than single-chip-level circuit complexity. Multiple chips have to be integrated with a technology that is reliable at cryogenic temperatures and supports an inter-chip data transmission speed of tens of GHz. In this work, we have studied two basic issues in building large RSFQ circuits. The first is the reliable inter-chip SFQ pulse transfer technique using Multi-Chip-Module (MCM) technology. By noting that the energy contained in an SFQ pulse is less than an attojoule, it is not very surprising that the direct transmission of a single SFQ pulse through MCM solder bump connectors can be difficult and an innovative technique is needed. The second is the recycling of the bias currents. Since RSFQ circuits are dc current biased the large RSFQ circuits need serial biasing to reduce the total amount of current input to the circuit.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.34D no.11
• /
• pp.1-8
• /
• 1997

In this paper, we propose a new method for the improvement of linearizing and adaptive convergence charateristics of the feedforward linear power amplifier. In this circuit, errors at the signal cancellation stage can be compensated at the error cancellation stage and the overall linearizaton and adaptation characteristics of the linear amplifier are improved. The broadband characteristics and linearizing capability are improved without increasing the complexity of circuits and the signal processing structure.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.8
• /
• pp.1-9
• /
• 1998

A new parallel test algorithm and a built-in self test (BIST) architecture are developed to test various types of functional faults efficiently in content addressable memories (CAMs). In test mode, the read oepratin is replaced by one parallel content addressable search operation and the writing operating is performed parallely with small peripheral circuit modificatins. The results whow that an efficient and practical testing with very low complexity and area overhead can be achieved.

• Journal of the Korean Operations Research and Management Science Society
• /
• v.22 no.1
• /
• pp.25-49
• /
• 1997

Printed circuit board (PCB) assembly line configuration is characterized by very long set-up times and high work in process (WIP) inventory level. The scheduling method can significantly reduce the set-up times and WIP inventory level. Greedy sequence dependent scheduling (GSDS) method is proposed based on the current methods. The proposed method is compared with the current method in terms of three performance measures: line throughput, average WIP inventory level, and implementation complexity.

• ETRI Journal
• /
• v.23 no.3
• /
• pp.138-149
• /
• 2001

Due to the rapidly growing complexity of VLSI circuits, test methodologies based on delay testing become popular. However, most approaches cannot handle custom logic blocks which are described by logic functions rather than by circuit primitive elements. To overcome this problem, a new path delay test generation algorithm is developed for custom designs. The results using benchmark circuits and real designs prove the efficiency of the new algorithm. The new test generation algorithm can be applied to designs employing intellectual property (IP) circuits whose implementation details are either unknown or unavailable.

• 전기의세계
• /
• v.31 no.1
• /
• pp.68-73
• /
• 1982

An accurate mathematical model of permanent magnet stepping motor is proposed. On the basis of this model, micro-stepping control is experimented. A comparison is made between the Data experimented by micro-stepping control and the data predicted by the proposed model and by Leenhouts' earlier model. The result shows that the proposed model is more accurate than the earlier model, and micro-stepping can be attained by dividing a given step electrically, without adding much complexity to the control circuit, or degrading the speed of stepping motors.

• Proceedings of the KIEE Conference
• /
• 2005.07a
• /
• pp.368-370
• /
• 2005

Due to the tendency towards large capacity and complexity of power system, an enhancement of power system equipment make a system impedance to be low in power system. Generally if an equivalent impedance of system becomes lower, a system stability will be better. But the fault current becomes very larger. The 345kV ultra-high voltage system will use current limit reactors(CLR) in a transmission line or a bus in substation to limit the magnitude of fault current. The CLR makes a significant contribution to the severity of the transient recovery voltage(TRV) experienced by feeder and bus circuit breakers on clearing feeder faults. Based on the conclusions of an investigation of actual circuit breaker failures while performing this duty, the mitigation of the transient recovery voltage associated with the reactors is described. Therefore in this article we simulated the TRV by EMTP at Bus Terminal Fault.