• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.500-504
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• 1997

Current source inverter drives of auto sequentially commutated type are very popular in high power applications, because of simple power circuit configuration with four quadrant operation. But the six-step current output create harmonic problems and the input power factor of such a drive is not always good. In this respect pulse width modulated drives using gate turn off thyristors ( GTO ) are finding application, especially in traction drives. However the switching and snubber loses of a GTO do not permit the inverter switching frequency go beyond a few hundred hertz.This will again introduce low frequency harmonic problems. Multi level inverters of the 3-level and 5-level can be considered as an alternative to overcome the low switching frequency harmonic problem of the 2-level GTO inverters. But with multi level inverters the complexity of the power circuit increases. In this paper a combination of multi level ( 2-level and 3-level ) inverters and multi phase induction motor ( 3-phase and 6-phase) configurations are presented for high power VSI drives for traction applications with reduced inverter switching frequency requirements coupled with reduced voltage rating for the power switch.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.72-79
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• 2003

Due to the improvements in circuit design technique and manufacturing technique, complexity of a circuit is growing along with the demand for memories with large capacities. Likewise, as a memory capacity gets larger, testing gets harder and testing cost increases, and testing process in chip development gets larger as well. Therefore, a research on an effective test algorithm to improve the chip yield rate in a short time period is becoming an important task. This paper proposes an effective, March C-algorithm based, test algorithm that can also be applied to a dual-port memory since it considers all the fault types, which can be occurred in a single-port as well as in a dual-port memory, without increasing the test length.

• The Bulletin of The Korean Astronomical Society
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• v.37 no.2
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• pp.228.1-228.1
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• 2012

Digital waveform generation technology for SAR payload can be divided into DDS(Direct Digital Synthesizer) method and Memory Mapped(M/M) method. DDS is the single chip which consists of the Sine Table, NCO(Numerically Controlled Oscillator), DAC, and so on. DDS method is a very simple method because the circuit configuration is not complex but has a disadvantage that can not control phase and amplitude easily by using NCO. M/M method has the complexity of the circuit configuration because it requires the memories which stores the waveforms, the control circuits, and DAC. And this method should apply the high interface technology for being compatible with the wide bandwidth of the digital signal and has the difficulty for PCB design because the number of the signal lines should be increased according to the number of the data bits for DAC. Although it has several disadvantages, this method has the capability of pre-distortion function which can compensate the phase and amplitude characteristics of the system and also has an excellent advantage to make any arbitrary waveform, so this method is considered as an important technology with DDS method. This research describes the technological trends of the waveform generator for the SAR payload and analyzes the characteristics of the technology.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.6
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• pp.550-559
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• 2005

The matrix converter provides sinusoidal input and output wave forms, bidirectional power flow, controllable input power factor and a long life, compared to the VSI(Voltage Source Inverter) with diode rectification stage at the input. However it has tasks, such as complexity of the control method, ride-through problem and low voltage-ratio limitation, to overcome for commercializing, This paper describes the design, construction and implementation of matrix converter based on space vector modulation technique. The implemented prototype of matrix converter is built using the exclusive IGBT module and control circuit constituted with DSP and CPLD and it has an input filter, overvoltage protection circuit and commutation means for overcoming practical issues. The good results tested using an induction motor are also presented.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.3
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• pp.219-226
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• 2011

As the existing contactless power transfer system(CPTS) is adopting the principle of contactless transformer enables to supply power in contactless way using RFID(radio frequency identification)/ID communication method between primary and secondary sides of contactless transformer and detect the alien load. Such CPTS requires the circuit that generates ID in addition, and the ID identification and control generated from the secondary side is performed at the primary side, which cuases complexity of the circuit. Therefore, this study suggested the CPTS using voltage phase, and In order to verify the validity of this study, 3[W] class CPTS shall be designed, and the simulation and test of CPTS using current and voltage phases shall be carried out.

• Journal of IKEEE
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• v.27 no.1
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• pp.12-18
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• 2023

The current circuit technology that individually connects each qubit to a control circuit at room temperature has limitations in achieving scalability and reliability of a quantum computer. With the advent of cryogenic CMOS interconnect electronics, it is expected to dramatically improve the interconnect complexity, system reliability and size, and price. In this paper, we introduce the CMOS integrated sensing and control technology platform overcoming the problems caused by the fragile and sensitive characteristics of qubit.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.47-55
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• 1999

In this paper, a new function hazard elimination algorithm is proposed for asynchronous circuit synthesis. In previous approach, function hazard is eliminated by using state graph which is obtained from the state assignment on STG(signal transition graph) representing transition relationship among signals. These algorithms can use conventional hazard removal and synthesis method applied in synchronous system, but it has much computational complexity and takes much time to handle the state graph. Although some hazard elimination algorithm from STG were proposed, it could not reduce the area overhead due to the addition of new signals. The proposed algorithm eliminate function hazard directly on STG and also control the number of minterms and product-term of added signal in order to minimize the area overhead. Experimental results on benchmark data shows that overall circuit area after hazard elimination is decreased about 15% on the average than that of previous method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.1-12
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• 2003

In this study, a regime where independent treatment of SETs in transient simulations is valid has been identified quantitatively. It is found that as in the steady-state case, each SET can be treated independently even in the transient case when the interconnection capacitance is large enough. However, the value of the load capacitance $C_{L}$of the interconnections for the independent treatment of SETs is approximately 10 times larger than that of the steady state case. A compact SET transient model is developed for transient circuit simulation by SPICE. The developed model is based on a linearized equivalent circuit and the solution of master equation is done by the programming capabilities of the SmartSpice. Exact delineation of several simulation time scales and the physics-based compact model make it possible to accurately simulate hybrid circuits in the time scales down to several tens of pico seconds. The simulation time is also shown to depend on the complexity level of the transient model.l.

• The Journal of the Convergence on Culture Technology
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• v.7 no.1
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• pp.558-563
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• 2021

Quantum-Dot Cellular Automata is a next-generation nanocircular design technology that is drawing attention from many research organizations not only because it is possible to design efficient circuits by overcoming the physical size limitations of existing CMOS circuits, but also because of its energy-efficient features. In this paper, one of the existing digital circuits, T flip-flop circuit, is proposed using QCA. The previously proposed T flip-flops are designed based on the majority gate, so the circuits are complex and have long delays. Therefore, the design of the XOR gate-based T flip-flop using cell interaction reduces circuit complexity and minimizes latency. The proposed circuit is simulated using QCADesigner, and the performance is compared and analyzed with the existing proposed circuits.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.459-461
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• 2022

One of the big differences between Network-on-Chip (NoC) and the existing parallel processing system based on an off-chip network is that data packet routing is performed using a centralized control scheme. In such an environment, the best-effort packet routing problem becomes a real-time assignment problem in which data packet arriving time and processing time is the cost. In this paper, the Hungarian algorithm, a representative computational complexity reduction algorithm for the linear algebraic equation of the allocation problem, is implemented in the form of a hardware accelerator. As a result of logic synthesis using the TSMC 0.18um standard cell library, the area of the circuit designed through case analysis for the cost distribution is reduced by about 16% and the propagation delay of it is reduced by about 52%, compared to the circuit implementing the original operation sequence of the Hungarian algorithm.