• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.338-343
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• 2006

This paper describes about the design concept and the architecture of an economic VPN system which can perform fast crypto operations with cheap cost. The essence of the proposed system architecture is consisting of the system with two companion chips dedicated to VPN: one chip is a multi-purpose network processor for security machine and the other is a crypto acceleration chip which encrypt and decrypt network packets in a high speed. This study also addresses about some realizations that is required for fast prototyping such as the porting of an operating system, the establishment of compiler tool chain, the implementation of device drivers and the design of IPSec security engine. Especially, the second chip supports the most time consuming block cipher algorithms including 3DES, AES, and SEED and its performance was evaluated.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.11a
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• pp.852-854
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• 2010

MCM-ERC32 는 우주 환경에서 동작하는 시스템에 사용할 목적으로 유럽에서 개발된 집약 프로세서 모듈이다. MCM (Multi Chip Module)은 크게 ERC32 single chip 과 VASI (Very Advanced Sparc Interface) 및 6MByte 의 SRAM, 32MByte 의 DRAM 으로 구성되어 있다. VASI 의 경우 각종 I/O 처리 및 timer 의 기능을 수행하며 특히 VASI RTC 의 경우 VASI cycle, slot 을 이용하여 다양한 형태의 timer 구현이 가능하다. Timer 의 경우 각종 태스크의 관리와 스케줄링에 사용되는 가장 기본적이며 매우 중요한 요소이다. 위성의 고유 시간 역시 timer 를 활용하여 설계하게 되는데 이 부분이 잘 구현 되어야 정확한 임무 수행 및 위성의 제어가 가능하다. 본 논문에서는 VASI RTC 의 구조와 기능에 대해 설명하고 이를 위성의 고유 시간 운영에 적용하는 방법에 대해 다루도록 하겠다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.3
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• pp.664-668
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• 2010

This paper presents a System-On-a-chip (SoC) for embedded image processing and pattern recognition applications that need Gaussian Pyramid structure. The system is fully implemented into Field-Programmable Gate Array (FPGA) based on the prototyping platform. The SoC consists of embedded processor core and a hardware accelerator for Gaussian Pyramid construction. The performance of the implementation is benchmarked against software implementations on different platforms.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.349-352
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• 2002

In this Paper, we introduced 32 bit SOC implementation for multi-application Smart Card and described the methodology for reducing power consumption. It consists of ARMTTDMI micro-processor, 192 KBytes EEPROM, 16 KB SRAM, crypto processors and card reader interface based on AMBA bus system. We used Synopsys Power Compiler to estimate and optimize power consumption. Experimental results show that we can reduce Power consumption up to 62 % without increasing the chip area.

• Journal of Korea Multimedia Society
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• v.19 no.7
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• pp.1154-1158
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• 2016

This paper presents a System-On-a-chip for embedded image processing applications that need Gaussian Pyramid structure. The system is fully implemented into Field-Programmable Gate Array (FPGA) based on the prototyping platform. The SoC consists of embedded processor core and a hardware accelerator for Gaussian Pyramid construction. The performance of the implementation is benchmarked against software implementations on different platforms.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.7
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• pp.354-360
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• 2008

Power-related issues have become important considerations in current generation microprocessor design. One of these issues is that of elevated on-chip temperatures. This has an adverse effect on cooling cost and, if not addressed suitably, on chip reliability. In this paper we investigate the general trade-offs between temporal and spatial hot spot mitigation schemes and thermal time constants, workload variations and microprocessor power distributions. By leveraging spatial and temporal heat slacks, our schemes enable lowering of on-chip unit temperatures by changing the workload in a timely manner with Operating System (OS) and existing hardware support.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2005.05a
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• pp.319-324
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• 2005

The interface between host processor and the ShortStack Micro Server may be a Serial Communication Interface(SCI). The LonWorks control module with a high performance is developed, which is composed of the 8 bit PIC Microprocessor for host processor and the smart neuron chip for the ShoretStack Micro Server. This intelligent control board is verified as proceeding the various function tests from experimental system with an boost pump and inverter driving systems. It is also confirmed that the developed control module provides stably 0-10VDC linear signal to the input signal of inverter driving system for varying the induction motor speed. Thus, the experimental results show that the fabricating intelligent board carried out very well the various functions in the wide operating ranges of boost pump system. This developed control module expect to apply to industrial fields to require the comparatively exact control and monitoring such as multi-motor driving system with inverter, variable air volume system and the boost pump water supply systems.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.141-151
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• 1994

this paper describes the design and implementation of a RISC processor for embedded control systems. This RISC processor integrates a register file, a pipelined execution unit, a FPU interface, a memory interface, and an instruction prefetcher. Its characteristics include both single cycle executions of most instructions in a 2 phase 20 MHz frequency and the worst case interrupt latency of 7 cycles with the vectored interrupt handling that makes it possible to be applicable to the real time processing system. For efficient handling of multi-cycle instructions, data stationary hardwired control scheme equippedwith cycle counter was used. This chip integrates about 139K transistors and occupies 9.1mm$\times$9.1mm in a 1.0um DLM CMOS technology. The power dissipation is 0.8 Watts from a 5V supply at 20 MHz operation.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.11
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• pp.34-43
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• 1999

A high-speed image processor (HIP) is implemented for a high-speed multi-function peripheral. HIP has a binarization architecture with unified data path. It has the pixel-by-pixel pipelined processing to minimize size of the external memory. It performs pre-processing such as shading correction, automatic gain control (AGC), and gamma correction, and also drives external CCD or CIS modules. The pre-processed data can be enlarged or reduced. Various binarizatin algorithms can be processed in the unified archiecture. The embedded binarization algorithms are simple thresholding, high pass filtering, dithering, error diffusion, and thershold modulated error diffusion. These binarization algorithms are unified based on th threshold modulated error diffusion. The data path is designed to share the common functional block of the binarization algorithms. The complexity of the controls and the gate counts is greatly reduced with this novel architecture.

• Journal of KIISE:Software and Applications
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• v.34 no.8
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• pp.697-707
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• 2007

Since embedded software is very dependent for target hardware architecture, characteristics of the platform must be considered when designing the software. Furthermore, MPSoCs consists of heterogeneous hardware components that are specified in micro level. Thus mapping of embedded software for MPSoCs should be considered the characteristics. In this paper, we provide an approach to automatic mapping PIM (Platform Independent Model) of an embedded software to PSM(Platform Specific Model) for MPSoC(Multi Processor System On Chip) and verify its effectiveness with simulation. In the proposed approach, tasks are derived from an object oriented model based on the UML (Unified Modeling Language). And then the types of the derived tasks are identified. With the identified types and inter relationship between tasks, the tasks are assigned to appropriate heterogeneous hardware components. We expect that the approach improve accuracy of the assigning and concurrency of the deployed software.