• JSTS:Journal of Semiconductor Technology and Science
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• 제9권3호
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• pp.174-180
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• 2009

A new flexible electronics technology, named P-FCB (Planar Fashionable Circuit Board), is introduced. P-FCB is a circuit board technology implemented on the plain fabric patch for wearable electronics applications. In this paper, the manufacturing of P-FCB, and its electrical characteristics such as sheet resistance, maximum current density, and frequency characteristics are reported. The fabrication methods and their electrical characteristics of passive devices such as resistor, capacitor, and inductor in P-FCB are discussed. In addition, how to integrate silicon chip directly to the fabric for the flexible electronics system are described. Finally, examples of P-FCB applications will be presented.

• 마이크로전자및패키징학회지
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• 제13권4호
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• pp.9-15
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• 2006

이 논문은 코어와 I/O 회로가 포함된 PEEC(Partial Equivalent Electrical Circuit) PDN(Power Distribution Networks)의 임피던스 변화에 따른 칩의 성능 분석을 나타내었다. I/O 전원에 연결된 코어 전원 잡음이 I/O 스위칭에 어떠한 영향이 미치는지 시뮬레이션 결과를 통하여 보였다. 또한 직접 설계한 $7{\times}5$인치 DLL(Delay Locked Loop)시험 보드를 사용하여 칩의 동작 지점에 따른 전원 잡음의 효과를 분석하였다. $50{\sim}400MHz$에 주파수 대역에 따른 DLL의 지터를 측정하고 시뮬레이션 결과로 얻어진 임피던스 값과 비교하였다. PDN의 공진 피크가 100MHz 주파수에서 1옴보다 큰 임피던스를 갖기 때문에 DLL의 지터는 주파수가 100MHz 근처에서 증가함을 보여준다. 타겟 임피던스를 줄이기 위한 방법인 디커플링 커패시터에 따른 칩과 보드의 임피던스 변화를 보였다. 따라서 전원 공급망 설계는 디커플링 커패시터와 함께 코어 스위칭 전류와 I/O 스위칭 전류를 같이 고려해야 한다.

• 한국정보통신학회논문지
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• 제24권4호
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• pp.508-514
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• 2020

LTE (Long Term Evolution) 및 5G와 같이 지속적으로 발전하는 이동 통신 표준을 구현하기 위해 소프트웨어 정의 라디오 (SDR, Software Defined Radio) 개념은 뛰어난 유연성과 효율성을 제공한다. 수년 동안, 최고급 디지털 시그널 프로세서 (DSP, Digital Signal Processor) 시스템 온 칩 (SoC, System on Chip)은 멀티 코어 및 다양한 하드웨어 보조 프로세서를 지원하는 방향으로 개발되어왔다. 이 논문에서는 TI의 TCI663x 칩을 사용해 구현한 SDR 플랫폼 하드웨어에 대해 소개하고, 이 플랫폼 상에서 멀티 코어 DSP를 BCP (Bit Rate Coprocessor) 및 TPC (Turbo Decoder Coprocessor)와 연동하여 구현한 LTE 전송 채널 (Transport Channel)의 성능을 다양한 구현 옵션에 따라 평가한다.

• 한국표면공학회지
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• 제43권3호
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• pp.142-147
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• 2010

We evaluated characteristics of ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) surface treatment for mobile equipment that requires high reliability, in addition to investigating surface treatment processes for semiconductor boards that require high reliability such as regular PCB-package systems, board-on-chip, chip-scaled package (CSP), etc and application for semiconductor package board of SIP, BOC. As a result, it appeared that ENEPIG has superior properties compared to ENIG surface treatment in corrosion resistance, solder junction, wetting, etc. We anticipate that these results will be able to lend credibility to ENEPIG as a low-cost alternative for producing mobile devices such as the cell phones, especially when applied to mass production.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.145-148
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• 2002

In a network communication process, cryptographic algorithms play important role for secure process. This paper presents a new system architecture named "DCCS." This system can handle flexible operations of both cryptographic algorithms and the keys. For experimental evaluation, two representative cryptographic algorithms DES and Triple-DES are designed and implemented into an FPGA chip on the SEBSW-1. Then the developed board is confirmed to change its cryptographic algorithms dynamically. Also its throughput confirmed the ability of the real-time net-work use of the designed system.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권4호
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• pp.543-551
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• 2017

SOL (Short, Open and Load) calibration based on iterative error sensitivity is proposed in this paper. With advanced SOL calibration, unknown parasitic parameters at on-chip terminations are accurately estimated up to 20 GHz. Artificial terminations are designed on printed circuit board (PCB) to experiment the proposed method. On-chip SHORT, OPEN and LOAD fabricated inside silicon shows the accuracy of proposed calibration method through the comparison with known fixture S-parameter after de-embedding.

• Journal of Mechanical Science and Technology
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• 제14권2호
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• pp.251-258
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• 2000

Thermal deformation in an electronic package due to thermal strain mismatch is investigated. The warpage and the in-plane deformation of the package after encapsulation is analyzed using the laminated plate theory. An exact solution for the thermal deformation of an electronic package with circular shape is derived. Theoretical results are presented on the effects of the layer geometries and material properties on the thermal deformation. Several applications of the exact solution to electronic packaging product development are illustrated. The applications include lead on chip package, encapsulated chip on board and chip on substrate.

• Transactions on Electrical and Electronic Materials
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• 제9권1호
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• pp.33-37
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• 2008

This paper describes the development of a new $5.0{\times}3.2mm$ SAW filter bank which is consist of 12 L, C matching components and 4 SAW bare chips on PCB substrate with CSP technology. We improved the manufacturing cost by removing the ceramic package through direct flip bonding of $LiTaO_3$ SAW bare chip on PCB board after mounting L, C passive element on PCB board. After that we realized the hermitic sealing by laminating the epoxy film. To confirm the confidentiality and durability of the above method, we have obtained the optimum flip bonding & film laminating condition, and figured out material property and structure to secure the durability & moisture proof of PCB board. The newly developed super mini $5.0{\times}3.2mm$ filter bank shows the superior features than those of existing products in confidence, electrical, mechanical characters.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• 한국전기전자재료학회논문지
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• 제26권6호
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• pp.493-501
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• 2013

LED lighting is sensitive because it made by semiconductor. So it has been researched about radiation of heat technologies for a long time. In addition, measurement and assessment a radiation of heat also conducted. It is necessary to get a date of accuracy temperature on the board after LED driven for measuring Junction temperature of the LED Lighting. For this research, we use 5 chip which is 4 W power on top of LED lighting board made by aluminum. Thermal camera effects to emissivity depending on material and property of the surface in LED board because it determines thermal energy which emitted from material surface. it is not only thermal camera has not a standard about emissivity. It has an error of temperature when emissivity was measured by thermal camera. we confirmed that emissivity and reflected temperature depending on color and quality of the surface throughout experiment.