• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.968-971
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• 2001

In this paper, internal antennas for IMT-2000 handset(1.92∼2.17 GHz) were designed to be capable of being mounted on the circuit-board with a CPW(coplanar waveguide) feeding structure. The chip antennas were miniaturized to a greater extent by fabricating multilayer high dielectric ceramic($\varepsilon$$\sub$r/=7.8) hexahedron. The proposed antennas has λ/4 monopole element with helical structure in the multilayer dielectric ceramic hexahedron. The simulated and measured results were invesgated with width, length, and thickness of helical structure in the hexahedron.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.4
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• pp.49-55
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• 2016

Nowadays there are magnetic sensors in a wide variety of equipment such as computers, cars, airplanes, medical and industrial instruments. In many of these applications the magnetic sensors offer safe and non-invasive means of detection and are more reliable than other technologies. The electric current in a conductor generates a magnetic field detected by this type of sensor. This work aims to define a package dedicated to an electrical current sensor using a MTJ (Magnetic Tunnel Junction) as a sensing device. Four different proposals of packaging, three variations of the chip on board (CoB) package type and one variation of the thin small outline package (TSOP) were analyzed by COMSOL modeling software by simulating a brad range of current injection. The results obtained from the thermal and magnetic analysis has proven to be very important for package improvements, specially for heat dissipation performance.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.5-8
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• 1999

In this paper, we suggest a way of implementing ISDN S-Interface through two-wire premises telephone networks instead of using four wires as in the existing ISDN systems. This will help many developing or underdeveloped countries in the world to introduce ISDN services, where they have only two or low wires as in-building telephone networks. We suggest new physical-layer specifications for two-wire S-interface similar to that in ITU-T recommendations I.430 for four-wire systems, design a tranceiver according to the suggested specifications, and implement it using an FPGA We build a test board with the chip on it and succeed in connecting to Internet.

• Journal of the Semiconductor & Display Technology
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• v.4 no.4 s.13
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• pp.27-31
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• 2005

This article contains the development of FPC bonder that used for repair or trial product. Nowadays, in FPO module process (including PDP) accept the thermo-compress bonding method when attach FPC(Flexible Printed Circuit Board), TCP(Tape Carrier Package) and COF(Chip on the FPC) by ACF(Anisotropic Conductive Film). This system consists of ACF attachment part, pre-bonding part, main bonding part, loading / unloading part. This composition is a stand-alone system, not an in-line system. Hereafter, this composition should be developing into in-line system in all area of FPD industry.

• Annual Conference of KIPS
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• 2002.11b
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• pp.1281-1284
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• 2002

본 논문은 인터넷을 이용한 음성통신 서비스를 제공하기 위해 사용되는 VoIP 시스템 칩 설계 및 기능 검증을 위한 보드 개발에 관한 것이다. 구성이 간단한 시스템을 구현하기 위하여 32 비트 RISC 프로세서인 ARM922T 프로세서 코어를 중심으로 IP 망 접속 기능, 톤 발생 및 음성신호 접속기능과 다양한 사용자 정합 기능을 가지는 VoIP 시스템 칩을 설계하고, 이 칩의 기능을 검증하기 위하여 시험 프로그램 및 통신 프로토콜을 개발하였으며, 각종 설계 및 시뮬레이션 툴을 사용하고 ARM922T와 FPGA가 결합된 Excalibur를 사용한 시험용 보드를 개발하여 시험하였다.

• Journal of the Semiconductor & Display Technology
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• v.18 no.3
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• pp.42-46
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• 2019

In this paper, we introduce the novel idea to improve parallel test efficiency of semiconductor test. The idea includes the test interface card consisting of NoC structure able to transmitting test data regardless of ATE speed. We called the scheme "Multi-Clock" mode. In the proposed mode, because NoC can spread over the test data in various rates, many semiconductors are tested in the same time. We confirm the proposed idea will be promising through a FPGA board test and it is important to find a saturation point of the Multi-Clock mode due to the number of test chips and ATE channels.

• Journal of Institute of Control, Robotics and Systems
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• v.16 no.2
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• pp.172-176
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• 2010

Recently, LCD (Liquid Crystal Display) requires various technical challenges; high definition, high quality, big size, and low price. These demands more pixels in the fixed area of the LCD and very fine lead pitch of the driving IC which controls the pixels. Therefore, a new packaging technology is needed to meet such technical requirement. NCP (Non Conductive Paste) is one of the new packaging methods and has excellent characteristics to overcome the problems of the ACF (Anisotropic Conductive Film). In this paper, we analyzed the process of the NCP for COF (Chip on FPCB) and proposed the key design parameters of the NCP process. Through a series of experiments, we obtained the stable values of the design parameters for successful NCP process.

• Journal of Advanced Marine Engineering and Technology
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• v.28 no.1
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• pp.46-55
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• 2004

Thermal characteristics of the various cooling methods in electronic equipment are studied numerically. A common chip cooling system is modeled as a parallel channel with protruding heat sources. A two-dimensional model has been developed for the numerical analysis of compressible. viscous. laminar flow. and conjugate heat transfer between parallel plates with uniform block heat sources. The finite volume method is used to solve this problem. The assembly consists of two channels formed by two covers and one printed circuit board that is assumed to have three uniform heat source blocks. Various cooling methods are considered to find out the efficient cooling method in a given geometry and heat sources. The velocity and the temperature fields. the local temperature distribution along the surface of blocks. and the maximum temperature in each block are obtained. The results are compared to examine the thermal characteristics of the different cooling methods both quantitatively and qualitatively.

• Proceedings of the KIEE Conference
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• summer
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• pp.363-365
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• 2004

This paper proposes a hardware implementation of intelligent electronic device for power transformer protection. And proposes an advanced main protection algorithm by voltage-current trend and flux-differential current slope characteristics. The secondary protection functions include UR, OCGR, OVR, and W etc. The main board of IED is based on the DSP chip TMS32C32 processor The IED was tested with relaying signals obtained for EMTP simulation package.

• Journal of the Semiconductor & Display Technology
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• v.17 no.1
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• pp.62-65
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• 2018

In the era of the 4th Industrial Revolution, IoT products of various and specialized fields are being developed and produced. Especially, the generation of the artificial intelligence, robotic technology Multilayer substrates and packaging technologies in the notebook, mobile device, display and semiconductor component industries are demanding the need for flexible materials along with miniaturization and thinning. To do this, this work use FCCL (Flexible Copper Clad Laminate), which is a flexible printed circuit board (PCB), to implement FPCB (Flexible PCB), COF (Chip on Film) Use is known to be essential. In this paper, I propose a transfer device which prevents the occurrence of scratches by analyzing the mechanism of wrinkle and scratch mechanism during the transfer process of thin film material in which the thickness increases while continuously moving in air or solution.