• Journal of the Korean Wood Science and Technology
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• 제15권3호
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• pp.44-55
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• 1987

In order to study the effect of sawdustboard combined with plastic chips, 0.5mm($T_1$), 1mm($T_2$), 1.4mm($T_3$) thick nylon fiber. polypropylene rope fiber(RP), and 0.23mm thick moth-proof polypropylene net fiber(NP) were cut into 0.5, 1, 2cm long plastic chips. Thereafter, sawdustboard combined with plastic chips prepared as the above and plastic non-combined sawdustboard(control) were manufactured into 3 types of one-, two-, and three layer with 5 or 10% combination level. By the discussions and results at this study, the significant conclusions of mechanical and physical properties were summarized as follows: 1. The MORs were shown in the order of 3 layer> 2 layer> 1 layer among plastic non-combined boards, and $T_3$ < $T_2$ < $T_1$ < RP (NP(5%) < NP(l0%) among plastic combined boards. In 2cm long plastic chip in 1 layer board, the highest strength through all the composition was recognized. 1 layer board showing the lower strength with 0.5cm plastic chip rendered to the bending strength improvement by 2 or 3 layer board composition. On the other hand, 2 or 3 layer combined with 1, 2cm long polypropylene net fiber chips incurred MOR's conspicuous decrease requiring optimum plastic chip combined level and consideration to combined type. 2. MOE in plastic non-combined 3 layer board exhibited sandwich construction effect by higher resin content application to surface layer in the order of 3layer>1layer>2layer with the highest stiffness of the board combined with polypropylene chip, while nylon chip-combined board had little difference from plastic non-combined board. In relevant to length and layer effect, 3 layer board combined with the 0.5cm long polypropylene net fiber chip in 5% and 10% combined level presented 34-43% and 44-76% stiffness increase against plastic non-combined board(control), respectively. Moreover, in 1 layer board, 30% stiffness increase with 10% against 5% combined level in the 1 and 2cm long polypropylene net fiber chip was obtained. 3. Stress at proportional limit(Spl) showing the fiber relationship (r: 0.81-0.97) between MOR presented in the order of 1 layer<2 layer<3 layer in plastic non-combined board. Correspondingly, combined effect by layer and plastic chip length was similar to MOR's. 4. Differently from previous properties(MOR, MOE, Spl). work to maximum load(Wml) of 2 layer board approached to that of 3 layer board. Conforming the above phenomenon. 2 layer combined with 0.5cm long polypropylene net fiber chip kept the greater work than 1 layer. The polypropylene combined board superior to nylon -and plastic non - combined board seemed to have greater anti - failing capacity. 5. Internal bond strength(IB), in contrast to MOR's tendency. showed in the order of T1

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2010년도 추계학술대회 논문집
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• pp.387-388
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• 2010

• 전자공학회논문지B
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• 제33B권2호
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• pp.149-158
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• 1996

In this paper we describe designing and implementing a digital neural chip and a parallel neural machine for simulating large scale neural netsorks. The chip is a single-chip multiprocessor which has four digiral neural processors (DNP-II) of the same architecture. Each DNP-II has program memory and data memory, and the chip operates in MIMD (multi-instruction, multi-data) parallel processor. The DNP-II has the instruction set tailored to neural computation. Which can be sed to effectively simulate various neural network models including on-chip learning. The DNP-II facilitates four-way data-driven communication supporting the extensibility of parallel systems. The parallel neural machine consists of a host computer, processor boards, a buffer board and an interface board. Each processor board consists of 8*8 array of DNP-II(equivalently 2*2 neural chips). Each processor board acn be built including linear array, 2-D mesh and 2-D torus. This flexibility supports efficiency of mapping from neural network models into parallel strucgure. The neural system accomplishes the performance of maximum 40 GCPS(giga connection per second) with 16 processor boards.

• 제어로봇시스템학회논문지
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• 제8권6호
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• pp.514-523
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• 2002

Feeder arrangement is an important element of process planning for printed circuit board assembly systems. This paper newly proposes a feeder arrangement method for multihead-gantry chip mounters. The multihead-gantry chip mounters are very popular in printed circuit board assembly system, but the research has been mainly focused on single-head-gantry chip mounters. We present an integer programming formulation for optimization problem of multihead-gantry chip mounters, and propose a heuristic method to solve the large NP-complete problem in reasonable time. Dynamic programming method is then applied to feeder arrangement optimization to reduce the overall assembly time. Comparative simulation results are finally presented to verify the usefulness of the proposed method.

• 전기학회논문지
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• 제59권9호
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• pp.1615-1620
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• 2010

A thin film thermoelectric cooler for COB direct assembly was proposed and the COB cooler structure was modeled by electrical equivalent circuit by using SPICE model of thermoelectric devices. The embedded cooler attached between the die chip and metal plate can offer the possibility of thin film active cooling for the COB direct assembly. We proposed a driving method of TEC by using pulse width modulation technique. The optimum power to the TEC is simulated by using a SPICE model of thermoelectric device and passive components representing thermal resistance and capacitance. The measured and simulated results offer the possibility of thin film active cooling for the COB direct assembly.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2011년도 춘계학술대회 논문집
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• pp.619-620
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• 2011

• 마이크로전자및패키징학회지
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• 제6권2호
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• pp.13-21
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• 1999

Flip chip assembly directly on organic boards offers miniaturization of package size as well as reduction in interconnection distances resulting in a high performance and cost-competitive Packaging method. This paper describes the investigation of alternative low cost flip-chip mounting processes using electroless Ni/Au bump and anisotropic conductive adhesives/films as an interconnection material on organic boards such as FR-4. As bumps for flip chip, electroless Ni/Au plating was performed and characterized in mechanical and metallurgical point of view. Effect of annealing on Ni bump characteristics informed that the formation of crystalline nickel with $Ni_3$P precipitation above $300^{\circ}C$ causes an increase of hardness and an increase of the intrinsic stress resulting in a reliability limitation. As an interconnection material, modified ACFs composed of nickel conductive fillers for electrical conductor and non-conductive inorganic fillers for modification of film properties such as coefficient of thermal expansion(CTE) and tensile strength were formulated for improved electrical and mechanical properties of ACF interconnection. The thermal fatigue life of ACA/F flip chip on organic board limited by the thermal expansion mismatch between the chip and the board could be increased by a modified ACA/F. Three ACF materials with different CTE values were prepared and bonded between Si chip and FR-4 board for the thermal strain measurement using moire interferometry. The thermal strain of ACF interconnection layer induced by temperature excursion of $80^{\circ}C$ was decreased with decreasing CTEs of ACF materials.

• 마이크로전자및패키징학회지
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• 제16권3호
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• pp.25-29
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• 2009

COB(chip-on-board) 플립칩 패키지에 있어서 NCP(non-conductive paste)의 적용성을 확보하기 위해 자체 포뮬레이션한 NCP와 상용 NCP에 대하여 보드레벨 플립칩 패키지를 제작하고 고온고습 및 열충격 신뢰성을 평가하였다. 실험결과 보다 작은 입도의 용융 실리카를 첨가한 NCP 시제품들이 고온고습 신뢰성에 유리한 것을 알 수 있었다. 또한, NCP 접속부에 있어서 열응력에 의한 피로보다 흡습에 의한 에폭시의 팽창이 접속부 파손에 보다큰 영향을 미치는 것으로 나타났으며, NCP의 접착강도가 높을수록 NCP 플립칩 패키지의 열충격 신뢰성이 향상되는 것을 알 수 있었다.

• 마이크로전자및패키징학회지
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• 제15권3호
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• pp.53-58
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• 2008

본 연구에서는 상용화된 2.4 GHz 영역대에서 사용되어지는 WiFi용 DPDT(Double Pole Double throw) switch 칩을 laser 비아 가공과 도금 공정을 이용하여 폴리머 기판내에 내장시켜 그 특성을 분석하였으며 통상적으로 실장되는 wire 본딩방식으로 패키징된 기판과 특성차이를 분석 비교하였다. 폴리머는 FR4기판과 아지노 모토사의 ABF(Ajinomoto build up film)를 이용하여 패턴도금법으로 회로를 형성하였다. ABF공정의 최적화를 위해 폴리머의 경화정토를 DSC (Differenntial Scanning Calorimetry) 및 SEM (Scanning Electron microscope)으로 분석하여 경화도에 따라 도금된 구리패턴과의 접착력을 평가하였다. ABF의 가경화도가 $80\sim90%$일 경우 구리층과 최적의 접착강도를 보였으며 진공 열압착공정을 통해 기공(void)없이 칩을 내장할 수 있었다. 내장된 기관과 와이어 본딩된 기판의 측정은 S 파라미터를 이용하여 삽입손실과 반사손실을 비교 분석하였으며 그 결과 삽입손실은 두 경우 유사하게 나타났지만 반사손실의 경우 칩이 내장된 경우 6 GHz 까지 -25 dB 이하로 안정적으로 나오는 것을 확인할 수 있었다.

• 한국전자파학회논문지
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• 제20권12호
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• pp.1264-1271
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• 2009

본 논문에서는 이동 무선 통신 기기에 적합하고 다중 대역에서 동작하도록 설계된 칩 슬롯 안테나를 제안하였다. 제안된 안테나는 시스템 회로 기판(30 mm$\times$60 mm$\times$0.8 mm) 위에 칩 안테나(10 mm$\times$20 mm$\times$1.27 mm)를 접속시킨 구조이며, 안테나의 F자 형태의 패턴의 끝단은 비아를 통해 시스템 회로 기판과 연결되어졌다. 따라서 칩 안테나는 시스템 회로 기판의 마이크로스트립 선로로부터 접지면 슬롯 사이의 전이(transition)를 통하여 효과적으로 에너지를 방사한다. 제작된 안테나의 측정 결과 3:1 VSWR 임피던스 대역폭($\leq$-6 dB)은 1.98 GHz(1.61~3.59 GHz)와 0.8 GHz(5.2~6 GHz)로 나타났다. 제안된 안테나는 DCS, PCS, UMTS, WLAN의 주파수 대역을 만족함으로 무선 통신 기기에 적용 가능할 것으로 사료된다.