• Journal of the Korean Wood Science and Technology
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• v.15 no.3
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• pp.44-55
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• 1987

In order to study the effect of sawdustboard combined with plastic chips, 0.5mm($T_1$), 1mm($T_2$), 1.4mm($T_3$) thick nylon fiber. polypropylene rope fiber(RP), and 0.23mm thick moth-proof polypropylene net fiber(NP) were cut into 0.5, 1, 2cm long plastic chips. Thereafter, sawdustboard combined with plastic chips prepared as the above and plastic non-combined sawdustboard(control) were manufactured into 3 types of one-, two-, and three layer with 5 or 10% combination level. By the discussions and results at this study, the significant conclusions of mechanical and physical properties were summarized as follows: 1. The MORs were shown in the order of 3 layer> 2 layer> 1 layer among plastic non-combined boards, and $T_3$ < $T_2$ < $T_1$ < RP (NP(5%) < NP(l0%) among plastic combined boards. In 2cm long plastic chip in 1 layer board, the highest strength through all the composition was recognized. 1 layer board showing the lower strength with 0.5cm plastic chip rendered to the bending strength improvement by 2 or 3 layer board composition. On the other hand, 2 or 3 layer combined with 1, 2cm long polypropylene net fiber chips incurred MOR's conspicuous decrease requiring optimum plastic chip combined level and consideration to combined type. 2. MOE in plastic non-combined 3 layer board exhibited sandwich construction effect by higher resin content application to surface layer in the order of 3layer>1layer>2layer with the highest stiffness of the board combined with polypropylene chip, while nylon chip-combined board had little difference from plastic non-combined board. In relevant to length and layer effect, 3 layer board combined with the 0.5cm long polypropylene net fiber chip in 5% and 10% combined level presented 34-43% and 44-76% stiffness increase against plastic non-combined board(control), respectively. Moreover, in 1 layer board, 30% stiffness increase with 10% against 5% combined level in the 1 and 2cm long polypropylene net fiber chip was obtained. 3. Stress at proportional limit(Spl) showing the fiber relationship (r: 0.81-0.97) between MOR presented in the order of 1 layer<2 layer<3 layer in plastic non-combined board. Correspondingly, combined effect by layer and plastic chip length was similar to MOR's. 4. Differently from previous properties(MOR, MOE, Spl). work to maximum load(Wml) of 2 layer board approached to that of 3 layer board. Conforming the above phenomenon. 2 layer combined with 0.5cm long polypropylene net fiber chip kept the greater work than 1 layer. The polypropylene combined board superior to nylon -and plastic non - combined board seemed to have greater anti - failing capacity. 5. Internal bond strength(IB), in contrast to MOR's tendency. showed in the order of T1

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.11a
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• pp.387-388
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• 2010

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.2
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• pp.149-158
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• 1996

In this paper we describe designing and implementing a digital neural chip and a parallel neural machine for simulating large scale neural netsorks. The chip is a single-chip multiprocessor which has four digiral neural processors (DNP-II) of the same architecture. Each DNP-II has program memory and data memory, and the chip operates in MIMD (multi-instruction, multi-data) parallel processor. The DNP-II has the instruction set tailored to neural computation. Which can be sed to effectively simulate various neural network models including on-chip learning. The DNP-II facilitates four-way data-driven communication supporting the extensibility of parallel systems. The parallel neural machine consists of a host computer, processor boards, a buffer board and an interface board. Each processor board consists of 8*8 array of DNP-II(equivalently 2*2 neural chips). Each processor board acn be built including linear array, 2-D mesh and 2-D torus. This flexibility supports efficiency of mapping from neural network models into parallel strucgure. The neural system accomplishes the performance of maximum 40 GCPS(giga connection per second) with 16 processor boards.

• Journal of Institute of Control, Robotics and Systems
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• v.8 no.6
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• pp.514-523
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• 2002

Feeder arrangement is an important element of process planning for printed circuit board assembly systems. This paper newly proposes a feeder arrangement method for multihead-gantry chip mounters. The multihead-gantry chip mounters are very popular in printed circuit board assembly system, but the research has been mainly focused on single-head-gantry chip mounters. We present an integer programming formulation for optimization problem of multihead-gantry chip mounters, and propose a heuristic method to solve the large NP-complete problem in reasonable time. Dynamic programming method is then applied to feeder arrangement optimization to reduce the overall assembly time. Comparative simulation results are finally presented to verify the usefulness of the proposed method.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.9
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• pp.1615-1620
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• 2010

A thin film thermoelectric cooler for COB direct assembly was proposed and the COB cooler structure was modeled by electrical equivalent circuit by using SPICE model of thermoelectric devices. The embedded cooler attached between the die chip and metal plate can offer the possibility of thin film active cooling for the COB direct assembly. We proposed a driving method of TEC by using pulse width modulation technique. The optimum power to the TEC is simulated by using a SPICE model of thermoelectric device and passive components representing thermal resistance and capacitance. The measured and simulated results offer the possibility of thin film active cooling for the COB direct assembly.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2011.06a
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• pp.619-620
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• 2011

• Journal of the Microelectronics and Packaging Society
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• v.6 no.2
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• pp.13-21
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• 1999

Flip chip assembly directly on organic boards offers miniaturization of package size as well as reduction in interconnection distances resulting in a high performance and cost-competitive Packaging method. This paper describes the investigation of alternative low cost flip-chip mounting processes using electroless Ni/Au bump and anisotropic conductive adhesives/films as an interconnection material on organic boards such as FR-4. As bumps for flip chip, electroless Ni/Au plating was performed and characterized in mechanical and metallurgical point of view. Effect of annealing on Ni bump characteristics informed that the formation of crystalline nickel with $Ni_3$P precipitation above $300^{\circ}C$ causes an increase of hardness and an increase of the intrinsic stress resulting in a reliability limitation. As an interconnection material, modified ACFs composed of nickel conductive fillers for electrical conductor and non-conductive inorganic fillers for modification of film properties such as coefficient of thermal expansion(CTE) and tensile strength were formulated for improved electrical and mechanical properties of ACF interconnection. The thermal fatigue life of ACA/F flip chip on organic board limited by the thermal expansion mismatch between the chip and the board could be increased by a modified ACA/F. Three ACF materials with different CTE values were prepared and bonded between Si chip and FR-4 board for the thermal strain measurement using moire interferometry. The thermal strain of ACF interconnection layer induced by temperature excursion of $80^{\circ}C$ was decreased with decreasing CTEs of ACF materials.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.25-29
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• 2009

High temperature high humidity and thermal shock reliability tests were performed for the board level COB(chip-on-board) flip chip packages using self-formulated and commercial NCPs(non-conductive pastes) to ensure the performance of NCP flip chip packages. It was considered that the more smaller fused silica filler in prototype NCPs is more favorable for high temperature high humidity reliability. The failure of NCP interconnection was affected by the expansion of epoxy due to moisture absorption rather than the fatigue due to thermal stress. It was considered that the NCP having more higher adhesive strength seems to be more favorable to increase the thermal shock reliability.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.3
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• pp.53-58
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• 2008

In this study, we fabricated embedded IC (Double Pole Double throw switch chip) polymer substrate and evaluate it for 2.4 GHz WiFi application. The switch chips were laminated using FR4 and ABF(Ajinomoto build up film) as dielectric layer. The embedded DPDT chip substrate were interconnected by laser via and Cu pattern plating process. DSC(Differenntial Scanning Calorimetry) analysis and SEM image was employed to calculate the amount of curing and examine surface roughness for optimization of chip embedding process. ABF showed maximum peel strength with Cu layer when the procuring was $80\sim90%$ completed and DPDT chip was laminated in a polymer substrate without void. An embedded chip substrate and wire-bonded chip on substrate were designed and fabricated. The characteristics of two modules were measured by s-parameters (S11; return loss and S21; insertion loss). Insertion loss is less than 0.55 dB in two presented embedded chip board and wire-bonded chip board. Return loss of an embedded chip board is better than 25 dB up to 6 GHz frequency range, whereas return loss of wire-bonding chip board is worse than 20 dB above 2.4 GHz frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.12
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• pp.1264-1271
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• 2009

In this paper, the chip slot antenna which is used for mobile devices and designed for multi-band is proposed. The proposed antenna is comprised of a chip antenna(10 mm$\times$20 mm$\times$1.27 mm) and a system circuit board(30 mm$\times$60 mm$\times$0.8 mm). The chip slot antenna is mounted on the system circuit board and the end of F-type strip line which is patterned on the chip antenna is connected by a via with a ground plane of the system circuit board. So, a chip antenna radiates effectively the energy by transition between a microstrip line of the system circuit board and a open slot structure of the chip antenna. In the results of proposed antenna, impedance bandwidth of 3:1 VSWR(-6 dB return loss) is 1.98 GHz(1.61~3.59 GHz) and 0.8 GHz(5.2~6 GHz). So, it can cover multi-band of DCS, PCS, UMTS, WLAN. The proposed antenna can be applied to mobile devices.