• Journal of Biosystems Engineering
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• 제30권3호
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• pp.161-165
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• 2005

In this study, peeling test of the Altari radish on kimchi pre-processing system for mechanization was performed with the longitudinal plane peeling type with wider cutting blade than that of the peeled chip's. To determine the optimum cutter shape to match this plane peeling type, the peeling tests depending on variable cutting speed, rake angle and blade angle using the blade with thickness as 2 m and width as 50mm were performed, and the patterns of the peeled chips and peeling resistances were investigated. As the result of the tests, the rake angle of the blade with clean peeled surface of the Altari radish was over $45^{\circ}$, and the blade angle and rake angle with the minimum peeling resistance was $20^{\circ}\;and\;60^{\circ}$, respectively. The optimum peeling conditions were; the peeling speed 0.2m/s, blade angle $20^{\circ}$ and the rake angle $60^{\circ}$, and the peeling resistance of each blade was 15 N.

• 한국생산제조학회지
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• 제20권2호
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• pp.187-192
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• 2011

UBM(Under Bump Metallurgy) is very important for successful realization of Flip-Chip technology. In this study, it is investigated the interfacial reactions between various Sn-Ag solder alloys and Ni-P/Au UBM and Cu plate finish. It is also evaluated the shear strength by using the micro shear-punch test method for Sn-37Pb alloy, binary and ternary alloys of environment-friendly Pb-free solder alloys which are applied in the electronic packages. In terms of interfacial microstructure, the Pb-free solder joints have thicker IMCs than the Sn-Pb solder joints. The thickness of IMC is related to Reflow time. The IMC has been observed to grow with the increase in Reflow time. As a result of the shear test, in case of Max. shear strength, Pb-free solder showed the highest strength value and Sn-37Pb showed the lowest strength value 10 be generally condition of Reflow time.

• 한국가시화정보학회:학술대회논문집
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• 한국가시화정보학회 2004년도 Proceedings of 2004 Korea-Japan Joint Seminar on Particle Image Velocimetry
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• pp.65-74
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• 2004

Measurement of concentration distributions of suspended particles in a micro-channel is out of the most crucial necessities in the area of Lab-on-a-chip to be used for various bio-chemical applications. One most feasible way to measure the concentration field in the micro-channel is using micro-LIF(Laser Induced Fluorescence) method. However, an accurate concentration field at a given cross plane in a micro-channel has not been successfully achieved so far due to various limitations in the light illumination and fluorescence signal detection. The present study demonstrates a novel method to provide an ultra thin laser sheet beam having five(5) microns thickness by use of a micro focus laser line generator. The laser sheet beam illuminates an exact plane of concentration measurement field to increase the signal to noise ratio and considerably reduce the depth uncertainty. Nile Blue A was used as fluorescent dye for the present LIF measurement. The enhancement of the fluorescent intensity signals was performed by a solvent mixture of water $(95\%)$ and ethanol (EtOH)/methanol (MeOH) $(5\%)$ mixture. To reduce the rms errors resulted from the CCD electronic noise and other sources, an expansion of grid size was attempted from $1\times1\;to\;3\times3\;or\;5\times5$ pixel data windows and the pertinent signal-to-noise level has been noticeably increased accordingly.

• Design & Manufacturing
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• 제2권2호
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• pp.25-28
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• 2008

Micro fabrication of biochip such like lab-on-a-chip becomes increasingly important. In this study, we designed and manufactured of new molds which were main factors for forming process in order to mass produce of biochip using forming process. Forming analysis of biochip was performed by Moldflow software. Results of this study are able to design and manufacture the mold which can be easy to eject the workpiece by using the slide mechanism for biochip.

• 한국표면공학회지
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• 제36권5호
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• pp.386-392
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• 2003

The electroplating process for a solder bump which can be applied for a flip chip was studied. Si-wafer was used for an experimental substrate, and the substrate were coated with UBM (Under Bump Metallization) of Al(400 nm)/Cu(300 nm)Ni(400 nm)/Au(20 nm) subsequently. The compositions of the bump were Sn-Cu and eutectic Sn-Pb, and characteristics of two bumps were compared. Experimental results showed that the electroplated thickness of the solders were increased with time, and the increasing rates were TEX>$0.45 <\mu\textrm{m}$/min for the Sn-Cu and $ 0.35\mu\textrm{m}$/min for the Sn-Pb. In the case of Sn-Cu, electroplating rate increased from 0.25 to $2.7\mu\textrm{m}$/min with increasing current density from 1 to 8.5 $A/dm^2$. In the case of Sn-Pb the rate increased until the current density became $4 A/dm^2$, and after that current density the rate maintains constant value of $0.62\mu\textrm{m}$/min. The electro plated bumps were air reflowed to form spherical bumps, and their bonded shear strengths were evaluated. The shear strength reached at the reflow time of 10 sec, and the strength was of 113 gf for Sn-Cu and 120 gf for Sn-Pb.

• 한국전자파학회지:전자파기술
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• 제24권2호
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• pp.51-57
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• 2013

The current expanding mobile markets incessantly demands small form factor, low power consumption and high aggregate throughput for silicon-level integration such as memory to logic system. One of emerging solution for meeting this high market demand is 3D through silicon stacking (TSS) technology. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. In addition, this technology inherently help increase number of IOs and shorten interconnect length. With those benefits, however, potential signal and power integrity risks are also elevated; increase in PDN inductance, channel loss on substrate, crosstalk and parasitic capacitance. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28 nm node TSV test vehicles were fabricated by the foundry and assembled. Successful integration of memory wide IO chip with less than a millimeter package thickness form factor was achieved. For this successful integration, we discussed potential signal and power integrity challenges. This report demonstrated functional wide IO memory to 28 nm logic device assembly using 3D package architecture with such a thin form factor.

• 한국기계가공학회지
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• 제18권10호
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• pp.75-82
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• 2019

Few studies have been conducted regarding theoretical turning force modelling while considering cutting constant. In this paper, a new cutting force modelling technique was suggested which considers the specific cutting force coefficients for turning. The specific cutting force is the multiplication of the cutting force coefficient and uncut chip thickness. This parameter was used for experimental modelling and prediction of theoretical cutting force. These coefficients, which can be obtained by fitting measured average forces in several conditions, were used for the formulation of three theoretical cutting forces for turning. The cutting force mechanism was verified in this research and its results were compared with each of the experimental and theoretical forces. The deviation of force was incurred by a small amount in this model and the predicted force considering feed rate, nose radius, and radial depth shows a physical behavior in main force, normal force, and feeding force, respectively. Therefore, this modelling technique can be used to effectively predict three turning forces with different tool geometries considering cutting force coefficients.

• 대한안전경영과학회지
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• 제17권3호
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• pp.355-362
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• 2015

There has been an increase of using Bosch Process to fabricate MEMS Device, TSV, Power chip for straight etching profile. Essentially, the interest of TSV technology is rapidly floated, accordingly the demand of Bosch Process is able to hold the prominent position for straight etching of Si or another wafers. Recently, the process to prevent under etching or over etching using EPD equipment is widely used for improvement of mechanical, electrical properties of devices. As an EPD device, the OES is widely used to find accurate end point of etching. However, it is difficult to maintain the light source from view port of chamber because of contamination caused by ion conflict and byproducts in the chamber. In this study, we adapted the SPOES to avoid lose of signal and detect less open ratio under 1 %. We use 12inch Si wafer and execute the through etching 500um of thickness. Furthermore, to get the clear EPD data, we developed an algorithm to only receive the etching part without deposition part. The results showed possible to find End Point of under 1 % of open ratio etching process.

• 센서학회지
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• 제28권1호
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• pp.1-6
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• 2019

This paper presents an air flow sensor (AFS) based on a polymer thin film. This AFS primarily consists of a polymer membrane attached to a metal-patterned glass substrate and a temperature-sensing element composed of NiCr. These two components were integrated on a single glass substrate. The AFS measures changes in capacitance caused by deformation of the polymer membrane based on the air flow and simultaneously detects the temperature of the surrounding environment. A readout integrated circuit (ROIC) was also fabricated for signal processing, and an ROIC chip, 1.8 mm by 1.9 mm in size, was packaged with an AFS in the form of a system-in-package module. The total size of the AFS is 1 by 1 cm, and the diameter and thickness of the circular-shaped polymer membrane are 4 mm and $15{\mu}m$, respectively. The rate of change of the capacitance is approximately 11.2% for air flows ranging between 0 and 40 m/s.

• 한국기계가공학회지
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• 제17권6호
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• pp.1-6
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• 2018

Recently nano meter size pattern (sub-micro scale) can be machined mechanically using a diamond tool. Many studies have found a 'size effect' which referred to a specific cutting energy increase with the decrease in the uncut chip thickness at micro scale machining. A new analysis method was suggested in order to observe 'size effect' in nano scale machining and to verify the cause of the 'size effect' in this study. The diamond tool was indented to a vertical depth of 1,000nm depth in order to simplify the stress state and the normal force was measured continuously. The tip rounding was measured quantitatively by AFM. Based on the measurements and theoretical analysis, it was verified that the main cause of the 'size effect' in nano scale machining is geometrically necessary dislocations, one of the intrinsic material characteristics. st before tool failure.