• Elastomers and Composites
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• 제58권2호
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• pp.87-94
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• 2023

Abrasion tests of an SBR compound were conducted using four different types of abrasion testers (cut and chip, Lambourn, DIN, and LAT100). The abrasion test results were analyzed in terms of size distributions and morphologies of the wear particles. Most wear particles were larger than 1000 ㎛. The wear particle size distributions tended to decrease as the particle size decreased. Except for the Lambourn abrasion test, the wear particles smaller than 212 ㎛ were rarely generated by the other three abrasion tests, implying that small wear particles were produced through friction by introducing talc powder. Shapes of the wear particles varied depending on the abrasion testers. The wear particles generated from the Lambourn abrasion tester had stick-like shapes. The cut and chip abrasion test showed a clear abrasion pattern, but the DIN abrasion test did not show any specific abrasion pattern. The Lambourn and LAT100 abrasion tests showed irregular abrasion patterns.

• 한국도로학회논문집
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• 제16권6호
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• pp.39-50
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• 2014

PURPOSES : The objective of this study is to evaluate the curing and adhesive behavior of asphalt emulsions including polymer-modified emulsions for chip seals and fog seals. METHODS : For the laboratory testing, the evaporation test, the bitumen bond strength (BBS) test, and the Vialit test are used. Also, the rolling ball test and the damping test are employed to evaluate the curing properties of the fog seal emulsions. In order to conduct all the tests in controled condition, all test procedures are performed in the environmental chamber. The CRS-2L and the SBS CRS-2P emulsions are used as a polymer-modified emulsion, and then unmodified emulsion, the CRS-2, is compared for the evaluation of chip seal performance. For the fog seal performance evaluation, two types of polymer-modified emulsions (FPME-1 and FPME-2) and one of unmodified emulsion, the CSS-1H, are employed. All the tests are performed at different curing times and temperatures. RESULTS AND CONCLUSIONS : Overall, PMEs show better curing and adhesive behavior than non-PMEs regardless of treatments types. Especially, the curing and adhesive behavior of PMEs is much better than non-PMEs before 120 minutes of curing time. Since all the test results indicate that after 120 minutes of curing time the curing adhesive behavior of emulsions, the early curing time, i.e., 120 minutes, plays an important role in the performance of chip seals and fog seals.

• 마이크로전자및패키징학회지
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• 제12권1호
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• pp.9-16
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• 2005

This paper presents the development of new anisotropic conductive adhesives with enhanced thermal conductivity for the wide use of adhesive flip chip technology with improved reliability under high current density condition. The continuing downscaling of structural profiles and increase in inter-connection density in flip chip packaging using ACAs has given rise to reliability problem under high current density. In detail, as the bump size is reduced, the current density through bump is also increased. This increased current density also causes new failure mechanism such as interface degradation due to inter-metallic compound formation and adhesive swelling due to high current stressing, especially in high current density interconnection, in which high junction temperature enhances such failure mechanism. Therefore, it is necessary for the ACA to become thermal transfer medium to improve the lifetime of ACA flip chip joint under high current stressing condition. We developed thermally conductive ACA of 0.63 W/m$\cdot$K thermal conductivity using the formulation incorporating $5 {\mu}m$ Ni and $0.2{\mu}m$ SiC-filled epoxy-bated binder system to achieve acceptable viscosity, curing property, and other thermo-mechanical properties such as low CTE and high modulus. The current carrying capability of ACA flip chip joints was improved up to 6.7 A by use of thermally conductive ACA compared to conventional ACA. Electrical reliability of thermally conductive ACA flip chip joint under current stressing condition was also improved showing stable electrical conductivity of flip chip joints. The high current carrying capability and improved electrical reliability of thermally conductive ACA flip chip joint under current stressing test is mainly due to the effective heat dissipation by thermally conductive adhesive around Au stud bumps/ACA/PCB pads structure.

• 경영과정보연구
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• 제34권3호
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• pp.125-140
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• 2015

본 연구에서는 현행 4부의 코스닥소속부제의 실효성을 검증하기 위해 현 제도에 따라 우량기업부로 구분된 기업집단을 대상으로 우량기업부 진입 전 후 기간의 이익조정 추세를 검토하였다. 구체적으로 2011년 현 소속부제의 시행에 따라 우량기업부에 진입한 111개 기업을 대상으로 우량기업부 진입 당해 연도와 진입 이전 이후 2개년을 포함한 총 5개 년도의 재량적 발생액과 실물이익조정치의 변화추이를 살펴보았다. 주요한 분석결과를 요약하면 다음과 같다. 먼저, 우량기업부에 소속된 기업만을 대상으로 우량기업부 편입 전 후 기간의 이익조정 추세를 검증한 결과 우량기업부 진입 직전 기간에 모든 이익조정 대용변수가 양(+)방향으로 크게 증가하며 그러한 이익조정치의 평균값이 통계적으로 유의하게 영(0)과 차이가 나는 것으로 나타났다. 또한, 우량기업부 진입 직전기간의 증가적 이익조정 현상이 이익조정에 영향을 미칠 수 있는 다양한 변인들을 통제한 다변량 분석체계에서도 다시금 입증되고 있음을 확인하였다. 이는 현행 소속부제의 평가시스템이 기업의 재무적 관점에 다소 편중되어 있어 내적가치가 부실한 기업이 우량기업부 진입을 통해 다양한 혜택을 누리고자 소속부 평가에 기초가 되는 우량기업부 진입 직전의 보고이익을 발생액 및 실물활동을 통해 광범위하게 증가시키는 경향이 있음을 보여준다. 이와 같은 본 연구의 결과는 증권시장에 대한 감독기관과 규제기관이 현행 소속부제의 공과 실을 면밀히 파악하여 부실기업과 우량기업을 보다 효과적으로 판별할 수 있는 제도적 장치의 마련을 강구하는 등 코스닥시장의 건전성 회복과 활성화를 위해 소속부제의 효익이 충분히 발휘될 수 있도록 운용의 묘를 살릴 필요가 있다는 정책적 시사점을 제공한다.

• 한국소음진동공학회논문집
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• 제11권8호
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• pp.331-337
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• 2001

The purpose of this study is to analyze the principal causes of vibration problem and find out the method of vibration reduction in a chip-mount system. The principal causes are investigated through measurements of vibration spectrum and model parameters. Modal parameters are obtained by using an experimental model test. Based on the model parameters from experiments. a model of finite element method is formulated. The model presents effective redesign of increasing the natural frequencies in order to reduce the vibration of a chip-mount system. Further, through computer simulation for the behavior of head to be main vibration source, the best acceleration pattern of head movement can be verified to achieve effective head-positioning and reduce the vibration due to head movement.

• 전기전자학회논문지
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• 제15권2호
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• pp.129-133
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• 2011

A spread spectrum clock generation is an efficient way to reduce electro-magnetic interference (EMI) radiation in modern mixed signal chip systems. The proposed circuit generates the spread spectrum clock by directly injecting the modulation voltage into the voltage-controlled oscillator (VCO) current source for SATA II. The resulting 33KHz modulation profile has a Hersey-Kiss shape with a rounded peak. The chip has been fabricated using $0.18{\mu}m$ CMOS process and test results show that the proposed circuit achieves 0.509% (5090ppm) down spreading at 1.5GHz and peak power reduction of 10dB. The active chip area is 0.36mm ${\times}$ 0.49mm and the chip consumes 30mW power at 1.5GHz.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(1)
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• pp.253-256
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• 2001

This paper describes a high speed MAC(Media Access Control) function chip for IEEE 802.11 MAC layer protocol. The MAC chip has control registers and interrupt scheme for interface with CPU and deals with transmission/reception of data as a unit of frame. The developed MAC chip is composed of protocol control block, transmission block, and reception block which supports the BCF function in IEEE 802.11 specification. The test suite which is adopted in order to verify operation of the MAC chip includes various functions, such as RTS-CTS frame exchange procedure, correct IFS(Inter Frame Space)timing, access procedure, random backoff procedure, retransmission procedure, fragmented frame transmission/reception procedure, duplicate reception frame detection, NAV(Network Allocation Vector), reception error processing, broadcast frame transmission/reception procedure, beacon frame transmission/reception procedure, and transmission/reception FIEO operation. By using this technique, it is possible to reduce the load of CPU and firmware size in high speed wireless LAN system.

• Journal of electromagnetic engineering and science
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• 제2권2호
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• pp.93-99
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• 2002

The Cartesian loop chip which is one of key devices in narrow-band Walky-Talky transmitter using RZ-SSB modulation method was designed and implemented with 0.35 Um CMOS technology. The reduced size and low cost of transmitter were available by the use of direct-conversion and Cartesian loop chip, which improved the power efficiency and linearity of transmitting path. In addition, low power operation was possible through CMOS technology. The performance test results of transmitter showed -23 dBc improvement of IMD level and -30 dEc below suppression of SSB characteristic in the operation of Cartesian loop chip (closed-loop). At that time, the transmitting power was about 37 dBm (5 W). The main parameters to improve the transmitting characteristic and to compensate the distortion in feed back loop such as DC-offset, loop gain and phase value are interfaced with notebook PC to be controlled with S/W.

• 한국기계가공학회지
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• 제18권1호
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• pp.101-108
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• 2019

In this study, the hole-cavity resonance technology and the micro pore stainless chip sintering technology were fused to develop silencers with excellent noise attenuation performance even at fluid pressures exceeding 30 bar for the first time at home and abroad. As a result of this study, the noise attenuation performance was greatly improved as reflection, loss, and resonance were made to occur thousands of times simultaneously when fluids pass through the sintered micro pore stainless steel chip sound absorber. The noise of the gas emitted from the bomb without the silencer was shown to be 125dB. And noise test conducted after installation of the silencer showed the noise of 67dB. Given the study results, the amount of noise was greatly reduced in the sintered silencer.

• Nuclear Engineering and Technology
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• 제55권3호
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• pp.1015-1020
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• 2023

A multi-layer design is applied to mitigate single event effect (SEE) in a 28 nm System-on-Chip (SoC). It depends on asymmetric multiprocessing (AMP), redundancy and system watchdog. Irradiation tests utilized 70 and 90 MeV proton beams to examine its performance through comparative analysis. Via examining SEEs in on-chip memory (OCM), compared with the trial without applying the multi-layer design, the test results demonstrate that the adopted multi-layer design can effectively mitigate SEEs in the SoC.