• Proceedings of the IEEK Conference
• /
• 2002.07c
• /
• pp.1571-1574
• /
• 2002

This paper describes a circuit and its operations of a programmable digital on-chip terminator designed with CMOS circuits which are used in high speed I/O interface. The on-chip terminator matches external reference resistor with the accuracy of ${\pm}$ 4.1％ over process, voltage and temperature variation. The digital impedance codes are generated in programmable impedance controller (PIC), and the codes are sent to terminator transistor arrays at input pads serially to reduce the number of signal lines. The transistor array is thermometer-coded to reduce impedance glitches during code update and it is segmented to two different blocks of thermometer-coded transistor arrays to reduce the number of transistors. The terminator impedance is periodically updated during hold time to minimize inter-symbol interferences.

• Proceedings of the KWS Conference
• /
• 2005.11a
• /
• pp.225-227
• /
• 2005

Sn-8wt%Zn-3wt%Bi (이하, Sn-8Zn-3Bi) 솔더의 장기 신뢰성을 평가하기 위하여 열 충격 시험을 행하였다. 열 충격 시험은 $-40^{\circ}C$에서 $80^{\circ}C$범위에서 1000 사이클 동안 하였다. 접합 기판으로는 각각 OSP(Organic Solderability Preservative), Sn 그리고 Ni/Au 처리를 한 PCB(Printed Circuit Board) 패드를 사용하였다. 접합에 사용한 부품은 1608 Chip(Multi Layer Chip Capacitor, Chip Resistor) 으로 전극 부위에 Sn-37wt%Pb, Sn 도금하여 사용하였다. 솔더링 후 1608 Chip의 전단 강도와 솔더링부에서 미세조직 및 IMC(Inter Metallic Compound) 변화를 관찰하였다. 측정결과, Sn-8Zn-3Bi 솔더의 초기 전단 강도는 기판의 표면처리에 상관없이 약 40N 이상이었다. 그리고 열충격 시험 1000 사이클 후에는 모든 기판에서 2N 정도 약간의 강도 저하를 보였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.28 no.3
• /
• pp.246-249
• /
• 2017

In this paper, we designed the 3-axis isotropic electric-field measurement probe using resistor-loaded short dipole with lumped chip resistors. The designed probe shows good isotropic characteristics as well as wideband and low sensitivity. The isotropic characteristics of ${\pm}0.39dB$ from 100 kHz to the 3 GHz band were derived and the reception sensitivity was 0.1 V/m. The frequency response is within 3 dB of the whole section, especially ${\pm}1.3dB$ from 150 kHz to 3 GHz, which is superior to the conventional electric field probe with short dipoles.

• Transactions on Electrical and Electronic Materials
• /
• v.8 no.5
• /
• pp.196-200
• /
• 2007

In this paper, we propose and discuss the design using a simple method that reduces the fixed pattern noise(FPN) generated on the amorphous Si($\alpha-Si$) bolometer. This method is applicable to an IR image sensor. This method can also minimize the size of the reference resistor in the readout integrated circuit(ROIC) which processes the signal of an IR image sensor. By connecting four bolometer cells in parallel and averaging the resistances of the bolometer cells, the fixed pattern noise generated in the bolometer cell due to process variations is remarkably reduced. Moreover an $\alpha-Si$ bolometer cell, which is made by a MEMS process, has a large resistance value to guarantee an accurate resistance value. This makes the reference resistor be large. In the proposed cell structure, because the bolometer cells connected in parallel have a quarter of the original bolometer's resistance, a reference resistor, which is made by poly-Si in a CMOS process chip, is implemented to be the size of a quarter. We designed a ROIC with the proposed cell structure and implemented the circuit using a 0.35 um CMOS process.

• Journal of Sensor Science and Technology
• /
• v.25 no.5
• /
• pp.349-353
• /
• 2016

Recently, research on bolometer-type uncooled infrared image sensor which is made for industrial applications has been increasing. In general, it is difficult to calibrate fixed pattern noise (FPN) of bolometer array. In this paper, average-current calibration algorithm is presented for reducing bolometer resistance offset. A resistor which is produced by standard CMOS process, on the average, has a deviation. We compensate for deviation of each resistor using average-current calibration algorithm. The proposed algorithm has been implemented by a chip which is consisted of a bolometer pixel array, average current generators, current-to-voltage converters (IVCs), a digital-to-analog converter (DAC), and analog-to-digital converters (ADCs). These bolometer-resistor array and readout circuit were designed and manufactured by $0.35{\mu}m$ standard CMOS process.

• Proceedings of the KIEE Conference
• /
• 2006.10c
• /
• pp.609-611
• /
• 2006

This paper describes a CMOS sub-bandgap reference using Pseudo-Resistors which can be widely used in flash memory, DRAM, ADC and Power management circuits. Bandgap reference circuit operates weak inversion for reducing power consumption and uses Pseudo-Resistors for reducing the chip area, instead of big resistor. It is implemented in 0.35um Standard 1P4M CMOS process. The temperature coefficient is 5ppm/$^{\circ}C$ from $40^{\circ}C$ to $100^{\circ}C$ and minimum power supply voltage is 1.2V The core area is 1177um${\times}$617um. Total current is below 2.8uA and output voltage is 0.598V at $27^{\circ}C$.

• Proceedings of the KIEE Conference
• /
• 2000.07c
• /
• pp.1794-1796
• /
• 2000

Oxides of the form $Mn_{3}O_4$-$Co_{3}O_4$-NiO present properties that make them useful as multilayer chip NTC thermistor for mobile communication telephone. When $Mn_{2}Ni_{x}CO_{1-x}O_4$ composition with the X = 0.12$\sim$0.24 at sintered temperature 1250$^{\circ}C$, resistivity and B-constant were 300$\sim$450[${\Omega}-cm$] and 3250$\sim$3450, respectively. Multilayer chip NTC(Negative Temperature Coefficient) resistor were fabricated with 4 layer by a conventional multilayer capacitor techniques, using 100 pd paste as internal electrode and $Mn_{2}Ni_{0.20}CO_{0.8}O_4$ composition as NTC materials. In particular, resistance change ratio (${\Delta}R$), the important factor for reliability, varied within $\pm$3%, indicating the compositions of multilayer chip NTC thermistor products could be available for mobile communication telephone.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.695-698
• /
• 1998

Today SOC(system on a chip) is a trend in VLSI design society. Especially MML(merged memory Logic) process provides designers with good chances to implement SOC which is consists of DRAM, SRAM, Logic and A/D mixed mode ciruit blocks. Designers need good circuit library which is reliable and easy to tune for specific design. For this need we present semi-automated analog compiler methodology. And we aplied this design methodology to resistor-string DAC design.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
• /
• 2001.11a
• /
• pp.189-194
• /
• 2001

본 논문에서는 10 GHz 이하에서 하나의 입력과 다수의 출력을 가지는 [10]에서 제시한 Taper형의 평면구조의 전력 분배/결합기의 구조를 수정하여 출력단의 폭이 다시 좁아지는 구조를 제안한다. 입력 정합 그리고 각 출력 단에서 출력 신호의 균형과 위상의 선형성을 위해 회로의 중앙에 하나의 원을 에칭 제거한 구조를 채택하여 2 GHz에서 개발한 전력 분배/결합구조를 [10]의 구조와 반사특성과 위상특성을 비교 분석하였다.

• Journal of IKEEE
• /
• v.23 no.1
• /
• pp.295-301
• /
• 2019

A heater in a portable real-time polymerase chain reaction(PCR) system is one of the important factors for controlling the PCR thermocycle precisely. Since heaters are integrated on a small-sized PCR chip for rapid heating and fabricated by semiconductor processes, the cost of producing PCR chips is high. Here, we propose to use chip resistors as an inexpensive and accurate temperature control method. The temperature distribution was simulated using one or two chip resistors on a real-time PCR chip and the PCR chip with uniform temperature distribution was fabricated. The temperature rise and fall rates were $18^{\circ}C/s$ and $3^{\circ}C/s$, respectively.