• Journal of the Korean Society of Safety
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• v.16 no.1
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• pp.88-93
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• 2001

This study discusses frequency analysis based on autoregressive (AR) time series model, and process characterization in orthogonal cutting of a fiber-matrix composite materials. A sparsely distributed idealized composite material, namely a glass reinforced polyester (GFRP) was used as workpiece. Analysis method employs a force sensor and the signals from the sensor are processed using AR time series model. The resulting pattern vectors of AR coefficients are then passed to the feature extraction block. Inside the feature extraction block, only those features that are most sensitive to different types of cutting mechanisms are selected. The experimental correlations between the different chip formation mechanisms and AR model coefficients are established.

• Journal of Microbiology and Biotechnology
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• v.16 no.1
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• pp.141-144
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• 2006

An antibody layer was fabricated to detect Escherichia coli O157:H7. The micropattern of 16-mercaptohexadecanoic acid (16-MHDA) as alkylthiolate was formed on the gold surface by using the PDMS stamp with microcontact printing $({\mu}CP)$ techniques. In order to form antibody patterns on the template, protein G was chemically bound to the 16-MHDA patterns, and antibody was adsorbed on a self-assembled protein G layer. The formation of the 16-MHDA micropattern, self-assembled protein G layer and antibody pattern on Au substrate was confirmed by surface plasmon resonance (SPR) spectroscopy. Finally, the micropatterning method was applied to fabricate the antibody probe for detection of E. coli O157:H7, and monitoring of antigen by using this probe was successfully achieved.

• Progress in Superconductivity
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• v.6 no.1
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• pp.7-12
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• 2004

Due to the very fast switching speed of Josephson junctions, superconductive digital circuit has been a very good candidate fur future electronic devices. High-speed and Low-power microprocessor can be developed with Josephson junctions. As a part of an effort to develop superconductive microprocessor, we have designed an RSFQ 4-bit ALU (Arithmetic Logic Unit) in a pipelined structure. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in this work consisted of three DC current driven SFQ switches and a half-adder. We successfully tested the half adder cell at clock frequency up to 20 GHz. The switches were commutating output ports of the half adder to produce AND, OR, XOR, or ADD functions. For a high-speed test, we attached switches at the input ports to control the high-speed input data by low-frequency pattern generators. The output in this measurement was an eye-diagram. Using this setup, 1-bit block of ALU was successfully tested up to 40 GHz. An RSFQ 4-bit ALU was fabricated and tested. The circuit worked at 5 GHz. The circuit size of the 4-bit ALU was 3 mm ${\times}$ 1.5 mm, fitting in a 5 mm ${\times}$ 5 mm chip.

• ETRI Journal
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• v.28 no.4
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• pp.475-485
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• 2006

Network-on-chip (NoC) is an emerging design paradigm intended to cope with future systems-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC-based SoCs. Among the existing test issues for NoC-based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC-based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC-based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC'02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC-based SoCs.

• Journal of the Korea Fashion and Costume Design Association
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• v.11 no.3
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• pp.101-110
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• 2009

Danchung(丹靑) is the traditional Korean patterns that are decorated with various colorful patterned paintings upon each sections of wooden architecture. Although Danchung consists of variety patterns with the meaningful signs and symbols, as an accomplishment of Korean traditional images, there is a few fashion merchandise by Danchung patterns. Therefore, the purpose of this study is about to design Jacquard fabrics, and to develop bags of Jacquard fabric by Danchung patterns, as a differentiated cultural Fashion Merchandise. The theoretical background was researched for the geometric image of Danchung patterns on the basis of the basic elements, compositions and symbolic meanings of Danchung. The geometric image of Danchung patterns, which had the shape of circle, triangle, square and hexagon, was designed to the surface design by Jacquard CAD system(i.e., EAT Designscope by Germany) and woven into Jacquard fabrics by Stabuli electronic Jacquard system. Danchung patterns for fabric design in this study was mainly focused on 'ChipJaGum', 'SamJiChangGum', 'ShouSulGum', Moro patterns of lotus flower(蓮花), Rok-Wha(綠花) and so on. To development bags of jacquard fabric, those woven jacquard fabrics were manufactured to bags by applying the selected of twelve bag-designs among the current bag styles. These manufactured bags of jacquard fabrics in geometric Danchung patterns were appeared a contemporary yet ethnic feeling so that they can be used for the unique korean cultural products to further commercialization.

• Proceedings of the Korean Institute of Building Construction Conference
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• 2011.05b
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• pp.105-109
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• 2011

This study is concerned with the development of the SL inorganic floor covering. First, volatile organic compounds, inorganic test profile on the SL through the flooring is environment-friendly inorganic noncombustible floor finishes the event of fire toxic gases (such as volatile organic compounds) emissions have been identified as not at all. Second, SL-breathable material, the concrete floor to prevent aging, long life, which are three levels of noise, shock-absorbing function was decreased. Third, SL economic analysis of mineral flooring terrazzo tile floors compared with the normal material. On a terrazzo tile cost 13,500 won ~ 24,500 won, but It have found that, in terms of labor SL 36,899 won ~ 38,899 won flooring mineral balance. Occurs in the total amount when compared with terrazzo tile floors and 25,399 won 3T, 5T and economical analysis concludes that the original 12,399 won.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.2
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• pp.135-140
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• 2014

In this paper, we describe the contents of noise characteristic enhancement using digital filtering to the motion vector in the pattern noise of optical mouse. The designed circuit is implemented to enhance the smoothing and trembling with filtering and averaging of x, y motion vector before PS2 or USB output. The function is verified by using FPGA and the performance is measured by the fabricated chip using $0.35{\mu}m$ standard CMOS process. The system clock is 6MHz and the motion vector has the range of +6 to -6 per 1/1700sec. It is tested using the Cartesian robot to measure the noise characteristic enhancement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.9-17
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• 2004

We present a performance improvement of Binary CDMA by flattening the correlation values. A Binary CDMA system, in which multi-leveled transmission signal of multi-code CDMA is clipped into a binary value, is cost-efficient since the strict linearity of the power amplifier is relieved. However, a loss of orthogonality among user channels due to the clipping causes the correlation values at the receiver to have a random distribution. If the correlation value for even a single channel goes too low, the average BER drops considerably. We developed a method of correlation flattening, where the binary chip pattern at the transmitter is adjusted so that the correlation values have averaged magnitude. Experimental results on several spreading codes show that the correlation flattening method increases the number of available channels at reduced BER.

• Journal of Korea Game Society
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• v.8 no.2
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• pp.57-68
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• 2008

Texture Mapping is a technique for adding realism to an image in 3D graphics Chip. Bilinear filtering mode of this technique needs accesses of 4 texels to process one pixel. In this paper we analyzed the access pattern of texture, and proposed the high performance texture cache which can access 4 texels simultaneously. We evaluated using simulation results of 3D game(Quake 3, Unreal Tournament 2004). Simulation results show that proposed texture cache has high performance on the case where physical size is less then or equal 8KBytes.

• Journal of the Korean Society for Nondestructive Testing
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• v.25 no.2
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• pp.81-86
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• 2005

This paper proposes a non-destructive ESPI technique to quantitatively evaluate defects inside a semiconductor package. The inspection system consists of the ESPI system, a thermal loading system and an adiabatic chamber. The technique is high feasibility for non-destructive testing of a semiconductor and overcomes the weaknesses of previous techniques, such as time-consumption and difficult quantitative evaluation. Most defects are classified as delamination defects, resulting from the insufficient adhesive strength between layers and from non-homogeneous heat spread. Ninety percent of the tested samples had delamination defects which originated at the corner of the chip and nay be related to heat spread design.