• 제목/요약/키워드: Chip pattern

검색결과 311건 처리시간 0.031초

2단계 고정화법을 이용한 DNA칩 마이크로어레이의 개발 (Development of DNA Chip Microarray by Using Secondary-step immobilization methods)

  • 윤희찬;김도균;신훈규;권영수
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2002년도 추계학술대회 논문집 전기물성,응용부문
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    • pp.263-265
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    • 2002
  • We have used the secondary-step immobilization methods based on the chip pattern of hydrophobic self-assembly layers to assemble microfabricated particles onto the chip pattern. Immobilization of DNA, fabrication of the particles and the chip pattern, arrangement of the particles on the chip pattern, and recognition of each using DNA fluorescence measurement were carried out. Establishing the walls, the arrangement stability of the particles was improved. Each DNA is able to distinguish by using the lithography process on the particles. Advantages of this method are process simplicity, wide applicability and stability. It is thought that this method can be applicable as a new fabrication technology to develop a minute integration type biosensor microarray.

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포물선 가감속 패턴을 가지는 정밀 펄스 모터 콘트롤러 칩의 설계 및 제작 (Design and Implementation of Parabolic Speed Pattern Generation Pulse Motor Control Chip)

  • 원종백;최성혁;김종은;박종식
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2001년도 합동 추계학술대회 논문집 정보 및 제어부문
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    • pp.284-287
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    • 2001
  • In this paper, we designed and implemented a precise pulse motor control chip that generates the parabolic speed pattern. This chip can control step motor[1], DC servo[2] and AC servo motors at high speed and precisely. It can reduce the mechanical vibration to the minimum at the change point of a degree of acceleration. Because the parabolic speed pattern has the continuous acceleration change. In this paper, we present the pulse generation algorithm and the parabolic pattern speed generation. We verify these algorithm using visual C++. We designed this chip with VHDL(Very High Speed Integrated Circuit Hardware Description Language) and executed a logic simulation and synthesis using Synopsys synthesis tool. We executed the pre-layout simulation and post-layout simulation with Verilog-XL simulation tool. This chip was produced with 100 pins, PQFP package by 0.35 um CMOS process and implemented by completely digital logic. We developed the hardware test board and test program using visual C++. We verify the performance of this chip by driving the servo motor and the function by GUI(Graphic User Interface) environment.

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범용 ${\mu}$-Processor와 One Chip으로 구현되는 유도전동기 구동 PWM Pattern에 관한 연구 (A Study on PWM Pattern for Driving Induction Motor using ${\mu}$-Processor and One Chip)

  • 황영민;허태원;박지호;신동률;조용길;우정인
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1998년도 추계학술대회 논문집 학회본부A
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    • pp.179-181
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    • 1998
  • In this paper, one chip PWM pattern generator which eliminates time delay of computations and improves utilization factor of voltage is proposed. Both amplitude of sinusoidal signal and triangular signal are directly controlled. Thus, time delay of computations can be eliminated, and it is possible to track accurately instantaneous current for a sudden change of load with microprocessor 80C196KC. In addition, setting dead-time is also possible for wide range. From experimental work with inverter system for driving induction motor, the validity of proposed one chip PWM pattern generator is verified.

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소수성 Template를 이용한 DNA Chip Microarray의 개발 (Development of DNA Chip Microarray Using Hydrophobic Template)

  • 최용성;박대희
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2004년도 추계학술대회 논문집 전기물성,응용부문
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    • pp.271-274
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    • 2004
  • Microarray-based DNA chips provide an architecture for multi-analyte sensing. In this paper, we report a new approach for DNA chip microarray fabrication. Multifunctional DNA chip microarray was made by immobilizing many kinds of biomaterials on transducers (particles). DNA chip microarray was prepared by randomly distributing a mixture of the particles on a chip pattern containing thousands of m-scale sites. The particles occupied a different sites from site to site. The particles were arranged on the chip pattern by the random fluidic self-assembly (RFSA) method, using a hydrophobic interaction for assembly.

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메모리 반도체 회로 손상의 예방을 위한 패키지 구조 개선에 관한 연구 (Appropriate Package Structure to Improve Reliability of IC Pattern in Memory Devices)

  • 이성민
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2002년도 하계학술대회 논문집
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    • pp.32-35
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    • 2002
  • The work focuses on the development of a Cu lead-frame with a single-sided adhesive tape for cost reduction and reliability improvement of LOC (lead on chip) package products, which are widely used for the plastic-encapsulation of memory chips. Most of memory chips are assembled by the LOC packaging process where the top surface of the chip is directly attached to the area of the lead-frame with a double-sided adhesive tape. However, since the lower adhesive layer of the double-sided adhesive tape reveals the disparity in the coefficient of thermal expansion from the silicon chip by more than 20 times, it often causes thermal displacement-induced damage of the IC pattern on the active chip surface during the reliability test. So, in order to solve these problems, in the resent work, the double-sided adhesive tape is replaced by a single-sided adhesive tape. The single-sided adhesive tape does net include the lower adhesive layer but instead, uses adhesive materials, which are filled in clear holes of the base film, just for the attachment of the lead-frame to the top surface of the memory chip. Since thermal expansion of the adhesive materials can be accommodated by the base film, memory product packaged using the lead-flame with the single-sided adhesive tape is shown to have much improved reliability. Author allied this invention to the Korea Patent Office for a patent (4-2000-00097-9).

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형태정합을 이용한 집적회로 패턴의 전체좌표 추출 (Global Coordinate Extraction of IC Chip Pattern Using Form Matching)

  • 안현식;조석제;이철동;하영호
    • 대한전자공학회논문지
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    • 제26권4호
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    • pp.120-126
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    • 1989
  • 최근 집적도의 증가와 더불어 집적회로 제작과 점검을 자동화하기 위하여 영상처리방법을 이용한 집적회로의 인식 알고리듬이 개발되고 있다. 집적회로를 인식하기 위해서는 프레임 영상으로 부터 특징을 얻고 이것으로써 칩내의 모든 프레임 영상을 정합하여야한다. 본 논문은 layout 정보를 나타내는 꼭지점들의 위치와 형태를 직선화 알고리듬을 이용하여 추출한다. 부분적으로 겹치는 이웃 프레임들을 얻어진 꼭지점의 위치와 형태를 특징으로 하여 정합함으로써 꼭지점의 전체적 좌표와 형태를 추출한다.

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신경망을 이용한 DNA칩 영상 패턴 분류 알고리즘 (Pattern Classification Algorithm of DNA Chip Image using ANN)

  • 주종태;김대욱;심귀보
    • 한국지능시스템학회논문지
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    • 제16권5호
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    • pp.556-561
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    • 2006
  • DNA칩 영상의 패턴 분류는 인간의 유전적 질병에 대한 유용한 정보를 획득할 수 있다는 점에서 아주 중요한 것이다. 본 논문에서는 DNA칩 영상의 패턴을 분류하기 위해 신경망의 학습 알고리즘 중 Back-propagation과 Self Organizing Map을 이용하여 패턴을 분류하는 알고리즘을 개발하고 이들의 결과를 비교 분석하였다. 또한 개발한 알고리즘은 PC 환경 및 S3C2440 (ARM920T)을 CPU Core로 사용한 MV2440 보드에서 실험하여 그 결과를 디스플레이 함으로써 사용자가 다양한 환경에서 보다 쉽게 유전자 정보를 얻는데 도움을 줄 수 있도록 하였다.

소수성 Template를 이용한 DNA칩의 제작 (Fabrication of DNA Chip Using a Hydrophobic Template)

  • 최용성;문종대;이경섭
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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    • pp.1315-1316
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    • 2006
  • Microarray-based DNA chips provide an architecture for multi-analyte sensing. In this paper, we report a new approach for DNA chip microarray fabrication. Multifunctional DNA chip microarray was made by immobilizing many kinds of biomaterials on transducers (particles). DNA chip microarray was prepared by randomly distributing a mixture of the particles on a chip pattern containing thousands of m-scale sites. The particles occupied a different sites from site to site. The particles were arranged on the chip pattern by the random fluidic self-assembly (RFSA) method, using a hydrophobic interaction for assembly.

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칩 마운트 시스템의 진동 경감 (Vibration Reduction of Chip-Mount System)

  • 임경화;장헌탁
    • 한국소음진동공학회논문집
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    • 제11권8호
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    • pp.331-337
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    • 2001
  • The purpose of this study is to analyze the principal causes of vibration problem and find out the method of vibration reduction in a chip-mount system. The principal causes are investigated through measurements of vibration spectrum and model parameters. Modal parameters are obtained by using an experimental model test. Based on the model parameters from experiments. a model of finite element method is formulated. The model presents effective redesign of increasing the natural frequencies in order to reduce the vibration of a chip-mount system. Further, through computer simulation for the behavior of head to be main vibration source, the best acceleration pattern of head movement can be verified to achieve effective head-positioning and reduce the vibration due to head movement.

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순동선삭가공에서 AE 신호를 이용한 칩 형상 제어 (Chip Shape Control using AE Signal in Pure Copper Turning)

  • 오정규;김평호;구준영;김덕환;김정석
    • 한국생산제조학회지
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    • 제23권4호
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    • pp.330-336
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    • 2014
  • The continuous chip generated in cutting process deteriorates workpiece, tool, and machine tool system. It is necessary to treat this continuous chip in ductile material machining condition for stable cutting. This paper deals with the chip control method using acoustic emission(AE) signal in pure copper turning operation. AE raw signals, root mean square(RMS) signals and wavelet transformed signals measured in turning process are introduced to analysis for chip patterns. With analysis of AE signals, it is obtained that the produced chip patterns are correlated with the specified AE signals which are transformed by fuzzy pattern algorithm. By this experimental investigation, the chip patterns can be classified at significant level in pure copper machining process and controlled from continuous chips to reduced-length stable chips.