• Journal of Powder Materials
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• v.22 no.3
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• pp.169-174
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• 2015

The optical film for light luminance improvement of BLU that is used in LCD/LED and retro-reflective film is used as luminous sign consist of square and triangular pyramid structure pattern based on V-shape micro prism pattern. In this study, we analyzed machining characteristics of Cu-plated flat mold by shaping with diamond tool. First, cutting conditions were optimizing as V-groove machining for the experiment of micro prism structure mold machining with prism pattern shape, cutting force and roughness. Second, the micro prism structure such as square and triangular pyramid pattern were machined by cross machining method with optimizing cutting conditions. Burr and chip shape were discussed with material properties and machining method.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.122-130
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• 2013

The demand and the supply are increasing sharply in accordance with the growth of the Memory Semiconductor Industry. The Flash Memory above all is being utilized substantially in the Industry of smart phone, the tablet PC and the System on Chip (SoC). The Flash Memory is divided into the NOR-type Flash Memory and the NAND-type Flash Memory. A lot of study such as the Built-In Self Test (BIST), the Built-In Self Repair (BISR) and the Built-In Redundancy Analysis (BIRA), etc. has been progressed in the NOR-type fash Memory, the study for the Built-In Self Test of the NAND-type Flash Memory has not been progressed. At present, the pattern test of the NAND-type Flash Memory is being carried out using the outside test equipment of high price. The NAND-type Flash Memory is being depended on the outside equipment as there is no Built-In Self Test since the erasure of block unit, the reading and writing of page unit are possible in the NAND-type Flash Memory. The Built-In Self Test equipped with 2 kinds of finite state machine based structure is proposed, so as to carry out the pattern test without the outside pattern test equipment from the NAND-type Flash Memory which carried out the test dependant on the outside pattern test equipment of high price.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.23 no.6
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• pp.609-617
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• 2014

We have studied a chip-on-board LED lighting optical system for various luminous-intensity-distribution angles of the LED. An optical system that can accept different LEDs was made to reduce the systems's weight and size as we selected the chip-on-board LED, which is easy to apply to optical systems, unlike existing package-on-board LEDs. The luminous-intensity-distribution angles were $45^{\circ}$, $60^{\circ}$, $90^{\circ}$, and $120^{\circ}$. We researched these four types of optical systems. The $45^{\circ}$ and $60^{\circ}$ units were developed into reflectors, and the $90^{\circ}$ and $120^{\circ}$ units, into lenses. We checked the performance of the designed optical system through simulation and made a mock-up. Then we made a prototype of the chip-on-board LED high bay for use with the mock-up. After measuring its performance, we tested the luminous-intensity-distribution angles and compared them with simulation data. The resulting prototype was developed considering brightness, light uniformity, age, and economics which are suitable for a factory environment.

• Journal of IKEEE
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• v.25 no.1
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• pp.180-192
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• 2021

One widely used algorithm for image recognition and pattern detection is the convolution neural network (CNN). To efficiently handle convolution operations, which account for the majority of computations in the CNN, we use hardware accelerators to improve the performance of CNN applications. In using these hardware accelerators, the CNN fetches data from the off-chip DRAM, as the massive computational volume of data makes it difficult to derive performance improvements only from memory inside the hardware accelerator. In other words, data communication between off-chip DRAM and memory inside the accelerator has a significant impact on the performance of CNN applications. In this paper, a simulator for the CNN is developed to analyze the main memory or DRAM access with respect to the size of the on-chip memory or global buffer inside the CNN accelerator. For AlexNet, one of the CNN architectures, when simulated with increasing the size of the global buffer, we found that the global buffer of size larger than 100kB has 0.8x as low a DRAM access count as the global buffer of size smaller than 100kB.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.4 s.310
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• pp.55-65
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• 2006

Most of fast block motion estimation algorithms reported so far in literatures aim to reduce the computation in terms of the number of search points, thus do not fit well with multimedia processors due to their irregular data flow. For multimedia processors, proper reuse of data is more important than reducing number of absolute difference operations because the execution cycle performance strongly depends on the number of off-chip memory access. Therefore, in this paper, we propose a Hexagon-shape line search (HEXSLS) algorithm using line search pattern which can increase data reuse from on-chip local buffer, and check sub-sampling points in line search pattern to reduce unnecessary SAD operation. Our experimental results show that the prediction error (MAE) performance of the proposed HEXSLS is similar to that of the full search block matching algorithm (FSBMA), while compared with the hexagon-based search (HEXBS), the HEXSLS outperforms. Also the proposed HEXSLS requires much lesser off-chip memory access than the conventional fast motion estimation algorithm such as the hexagon-based search (HEXBS) and the predictive line search (PLS). As a result, the proposed HEXSLS algorithm requires smaller number of execution cycles on media processor.

• Journal of Korea Society of Digital Industry and Information Management
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• v.10 no.4
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• pp.79-87
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• 2014

In this paper, we implemented the HearCAM platform with Raspberry PI B+ model which is an open source platform. Raspberry PI B+ model consists of dual step-down (buck) power supply with polarity protection circuit and hot-swap protection, Broadcom SoC BCM2835 running at 700MHz, 512MB RAM solered on top of the Broadcom chip, and PI camera serial connector. In this paper, we used the Google speech recognition engine for recognizing the voice characteristics, and implemented the pattern matching with OpenCV software, and extended the functionality of speech ability with SVOX TTS(Text-to-speech) as the matching result talking to the microphone of users. And therefore we implemented the functions of the HearCAM for identifying the voice and pattern characteristics of target image scanning with PI camera with gathering the temperature sensor data under IoT environment. we implemented the speech recognition, pattern matching, and temperature sensor data logging with Wi-Fi wireless communication. And then we directly designed and made the shape of HearCAM with 3D printing technology.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1169-1172
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• 1998

We designed an ALU(Airthmetic Logic Unit) with BIST(Built-In Self Test), which is suitable for 32-bit DSP RISC processors. We minimized the area of this ALU by allowing different operations to share several hardware blocks. Moreover, we applied DFT(Design for Testability) to ALU and offered Bist(Built-In Self-Test) function. BIST is composed of pattern generation and response analysis. We used the reseeding method and testability design for the high fault coverage. These techniques reduce the test length. Chip's reliability is improved by testing and the cost of testing system can be reduced.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.3
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• pp.664-668
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• 2010

This paper presents a System-On-a-chip (SoC) for embedded image processing and pattern recognition applications that need Gaussian Pyramid structure. The system is fully implemented into Field-Programmable Gate Array (FPGA) based on the prototyping platform. The SoC consists of embedded processor core and a hardware accelerator for Gaussian Pyramid construction. The performance of the implementation is benchmarked against software implementations on different platforms.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.7
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• pp.1069-1072
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• 2002

고도로 발달된 정보화 시대에서 우리가 원하는 정보를 짧은 시간, 적은 비용으로 서로 주고 받기 위해서는 이것에 맞는 시스템이 요구된다. 반도체 chip의 대용량과 고속화됨으로써 TTL, ,LVTTL등이 data 100Mbps 정도를 안전하게 전달 할 수 있는 능력이 있으므로 그 이상을 전달할 수 있는 새로운 Logic level이 필요하게 되었다. 이에 맞추어 신호 level의 여러 가지 중 본 논문에서는 Virtex II XC2V 1000 FF896을 이용하여 Differential I/O LVDS( Low Voltage Differential Signaling ) level 특성을 clock, Data와의 전송관계를 Eye_Pattern을 통해 살펴보았다.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.42.4-42
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• 2002

With the research of simplified neural networks, we propose an AND/OR neural network; a kind of brief, fast network Then, we present an OCR solution that equip the network in one-chip FPGA and design it by using HDL. We selected the representative hexadecimal character as the recognition feature class and used a Feature Vector Recognition Method in the statistic pattern recognition. The result feature vector was encoded into a 7 bit array and inputted into the AND/OR network to finish learning.