• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 1999년도 추계학술대회 논문집 - 한국공작기계학회
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• pp.513-518
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• 1999

In this study, geometrical similarity conditions for drills of various diameters are discussed. The effect of geometrical similarity on the chip shape and forces of different sized conventional drills has been experimentally confirmed. Drilling tests are carried out for SM45C by using the conventional HSS drills. The torque and thrust forces are measured and compared with those chip forms. Chip shape in drilling are affected by three factors being flow angle, side and up curl of the chip. It is found that the feedrate and drill diameter are more affected than cutting speed on the chip form and cutting forces. The similarity conditions gives easily to estimate the chip shape, the thrust and the torque for drills of different diameters.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.404-405
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• 2006

Microarray-based DNA chips provide an architecture for multi-analyte sensing. In this paper, we report a new approach for DNA chip microarray fabrication. Multifunctional DNA chip microarray was made by immobilizing many kinds of biomaterials on transducers (particles). DNA chip microarray was prepared by randomly distributing a mixture of the particles on a chip pattern containing thousands of m-scale sites. The particles occupied a different sites from site to site. The particles were arranged on the chip pattern by the random fluidic self-assembly (RFSA) method, using a hydrophobic interaction for assembly.

• 마이크로전자및패키징학회지
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• 제25권1호
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• pp.1-10
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• 2018

최근 플렉서블 OLED, 플렉서블 반도체, 플렉서블 태양전지와 같은 유연전자소자의 개발이 각광을 받고 있다. 유연소자에 밀봉 혹은 봉지(encapsulation) 기술이 매우 필요하며, 봉지 기술은 유연소자의 응력을 완화시키거나, 산소나 습기에 노출되는 것을 방지하기 위해 적용된다. 본 연구는 봉지막(encapsulation layer)이 반도체 칩의 내구성에 미치는 영향을 고찰하였다. 특히 다층 구조 패키지의 칩의 파괴성능에 미치는 영향을 칩의 center crack에 대한 파괴해석을 통하여 살펴보았다. 다층구조 패키지는 폭이 넓어 칩 위로만 봉지막이 덮고있는 "wide chip"과 칩의 폭이 좁아 봉지막이 칩과 기판을 모두 감싸고 있는 "narrow chip"의 모델로 구분하였다. Wide chip모델의 경우 작용하는 하중조건에 상관없이 봉지막의 두께가 두꺼울수록, 강성이 커질수록 칩의 파괴성능은 향상된다. 그러나 narrow chip모델에 인장이 작용할 때 봉지막의 두께가 두껍고 강성이 커질수록 파괴성능은 악화되는데 이는 외부하중이 바로 칩에 작용하지 않고 봉지막을 통하여 전달되기에 봉지막이 강하면 강한 외력이 칩내의 균열에 작용하기 때문이다. Narrow chip모델에 굽힘이 작용할 경우는 봉지막의 강성과 두께에 따라 균열에 미치는 영향이 달라지는데 봉지막의 두께가 작을 때는 봉지막이 없을 때보다 파괴성능이 나쁘지만 강성과 두께의 증가하면neutral axis가 점점 상승하여 균열이 있는 칩이 neutral axis에 가까워지게 되므로 균열에 작용하는 하중의 크기가 급격히 줄어들게 되어 파괴성능은 향상된다. 본 연구는 봉지막이 있는 다층 패키지 구조에 다양한 형태의 하중이 작용할 때 패키지의 파괴성능을 향상시키기 위한 봉지막의 설계가이드로 활용될 수 있다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.115-118
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• 2002

This paper presents the design method and performance characteristics of a chip-type quadrature hybrid using LTCC-MLC technology. The design method for a chip-type quadrature hybrid is based on lumped element equivalent circuit of quarter-wave transformer. The chip-type quadrature hybrid was miniaturized to a greater extent using multilayer structure and lumped element. The proposed design method can also reduce the undesirable parasitic effects of the chip-type quadrature hybrid. The proposed chip-type quadrature hybrid was designed and fabricated using the proposed design method and the equivalent circuit model of a quarter-wave transformer. Fabrication and measurement of designed chip-type quadrature hybrid show much smaller size than a conventional distributed quadrature hybrid and a good agreement with simulated results.

• 한국도로학회논문집
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• 제15권2호
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• pp.65-71
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• 2013

PURPOSES : The objective of this study is to evaluate the effect of physical characteristics of emulsion asphalt and aggregate on performance of chip seal pavements. METHODS : In order to evaluate the performance of chip seal materials, the sweep tests and Vialit Plate Shock tests were conducted on the mixtures with five emulsion asphalt binders and three aggregate types. The sweep tests was intended to investigate the change of bonding properties between emulsion asphalt and aggregate with curing time. The Vialit Plate Shock test was used to evaluate the bonding properties of chip seal materials at low temperatures. RESULTS : Results from sweep tests showed that polymer modified emulsion asphalt can reduce the curing time by 1.5 hour comparing with typical emulsion asphalt. It is also found that the Flakiness Index of aggregates and absorption rate of binder are the major factors affecting the bonding properties of chip seal materials. The Vialit Plate Shock test results showed that the average aggregate loss of CRS-2 is ten times higher than CRS-2P No.2 indicating that the use of polymer additives in emulsion asphalt can improve the performance of chip seal materials in low temperature region. CONCLUSIONS : The use of polymer in emulsion asphalt can decrease the curing time of chip seal materials and increase the bonding properties between aggregates and asphalt binder. It is also concluded that the lower Flakiness Index and absorption rate of aggregates can improve the performance of chip seal pavement.

• 대한전자공학회논문지
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• 제18권4호
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• pp.34-42
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• 1981

PMOS집적기술을 이용하여 512-Bit mask programmable ROM을 설계하고 제작하였다. ROM의 내용은 제작공정에서 gate pattern으로 기억시켰으며 chip의 출력을 512(32×16)개의 점의 행렬로써 오실로스코프에 나타내어 확인하였다. 제작된 chip은 -6V와 - l2V의 범위에서 정상적으로 동작하였다 소모전력과 전달지연시간은 -6V에서 각각 3mW와 13μsec였다. -12V에서는 소모전력이 27mW로 증가하였으며 전달지연시간은 3μsec로 감소하였다. Chip의 출력은 TTL gate의 인력을 직접 구동시킬 수 있었으며 chip select에 의하여 출력을 disable 시켰을 때는 높은 임피던스 상태를 유지하였다.

• 마이크로전자및패키징학회지
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• 제18권1호
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• pp.41-47
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• 2011

Currently, there is widespread adoption of silicon-based technologies for the implementation of radio frequency (RF) integrated passive devices (IPDs) because of their low-cost, small footprint and high performance. Also, the need for high speed data transmission and reception coupled with the ever increasing demand for mobility in consumer devices has generated a great interest in low cost devices with smaller form-factors. The UWB BPF makes use of lumped IPD technology on a silicon substrate CSMP (Chip Scale Module Package). In this paper, this filter shows 2.0 dB insertion loss and 15 dB return loss from 7.0 GHz to 9.0 GHz. To the best of our knowledge, the UWB band-pass-filter developed in this paper has the smallest size ($1.4\;mm{\times}1.2\;mm{\times}0.40\;mm$) while achieving equivalent electrical performance.

• ETRI Journal
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• 제19권3호
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• pp.228-241
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• 1997

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMs, and the chip size is $10 mm{\times}10.1 mm$ which is fabricated using a $0.8{\mu}m$ 2 metal CMOs technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32K ($2k{\times}16\;bit$) RAM, and 240k ($10k{\times}24\;bit$) ROM. The die size is $8.7\;mm{\times}8.3\;mm$ and chip is fabricated using $0.8\;{\mu}m$ CMOS technology.

• 전기전자학회논문지
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• 제23권4호
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• pp.1203-1207
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• 2019

As the number of IP cores has been increasing in a System-on-Chip (SoC), multiple routers are included in on-chip-networks. Each router has its own arbitration policy and it is difficult to obtain a desired arbitration result by combining multiple routers. Allocating desired bandwidths to the ports across the routers is more difficult. In this paper, a guaranteed bandwidth allocation scheme using an IP-level QoS control is proposed to overcome the limitations of existing local arbitration policies. Each IP can control the priority of a packet depending on the data communication requirement within the allocated bandwidth. The experimental results show that the proposed mechanism guarantees for IPs to utilize the allocated bandwidth in multiple router on-chip-networks. The maximum error rate of bandwidth allocation of the proposed scheme is only 1.9%.

• 마이크로전자및패키징학회지
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• 제27권4호
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• pp.1-10
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• 2020

웨어러블 소자를 구현하기 위한 칩-섬유 접합 기술을 중심으로 전자 섬유에 대한 기술 개발 동향을 소개한다. 전자 부품을 섬유에 접합하기 위해서는 먼저 전자 부품에 전원 공급 및 전기적 신호를 주고 받기 위한 회로를 섬유에 구성해야 하며, 회로의 해상도와 밀도에 따라 전도성 실을 이용하는 자수법 또는 전도성 페이스트 등을 이용한 프린트법을 통해 구현할 수 있다. 전자 부품과 섬유를 접합하기 위해서는 솔더링, ACF/NCA, 자수법, 크림핑 등의 방법을 이용하여 영구적으로 접합하거나 후크, 자석, 지퍼 등을 이용하여 탈부착이 가능하도록 접합하는 방법이 있으며, 접합 배선의 밀도 및 용도에 따라서 단독 또는 융합하여 사용한다. 접합 이후에는 방수 등 사용환경에서의 신뢰성을 확보하기 위해 encapsulation 작업을 수행해야 하며, 현재는 PDMS 등의 폴리머를 이용한 방법이 널리 쓰이고 있다.