• Proceedings of the Korean Society of Precision Engineering Conference
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• 한국정밀공학회 1995년도 추계학술대회 논문집
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• pp.151-156
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• 1995

This paper presents a methodology for real-time detecting and identifying the runout geometry of an end mill. Cutter runout is a common but undesirable phenomenon in multi-tooth machining such as end-milling process because it introduces variable chip loading to insert which results in a accelerated tool wear,amplification of force variation and hence enlargement vibration amplitude. Form understanding of chip load change kinematics, the analytical sutting force model was formulated as the angular domain convolution of three dynamic cutting force component functions. By virtue of the convolution integration property, the frequency domain expression of the total cutting forces can be given as the algebraic multiplication of the Fourier transforms of the local cutting forces and the chip width density of the cutter. Experimental study are presented to validata the analytical model. This study provides the in-process monitoring and compensation of dynamic cutter runout to improve machining tolerance tolerance and surface quality for industriql application.

• IEIE Transactions on Smart Processing and Computing
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• 제4권2호
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• pp.65-70
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• 2015

In this paper, we describe the world's first real-time ray-tracing chip architecture. Ray-tracing technology generates high-quality 3D graphics images better than current rasterization technology by providing four essential light effects: shadow, reflection, refraction and transmission. The real-time ray-tracing chip named RayChip includes a real-time ray-tracing graphics processing unit and an accelerating tree-building unit. An ARM Ltd. central processing unit (CPU) and other peripherals are also included to support all processes of 3D graphics applications. Using the accelerating tree-building unit named RayTree to minimize the CPU load, the chip uses a low-end CPU and decreases both silicon area and power consumption. The evaluation results with RayChip show appropriate performance to support real-time ray tracing in high-definition (HD) resolution, while the rendered images are scaled to full HD resolution. The chip also integrates the Linux operating system and the familiar OpenGL for Embedded Systems application programming interface for easy application development.

• Journal of Power Electronics
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• 제16권3호
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• pp.1209-1217
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• 2016

This paper presents a novel charge pump scheme that combines the advantages of Fibonacci and Dickson charge pumps to obtain 30 V voltage for display driver integrated circuit application. This design only requires four external capacitors, which is suitable for a small-package application, such as smart card displays. High-amplitude (<6.6 V) clocks are produced to enhance the gate drive of a Dickson charge pump and improve the system's current drivability by using a voltage-doubler charge pump with a pulse skip regulator. This regulation engages many middle-voltage devices, and approximately 30% of chip size is saved. Further optimization of flying capacitors tends to decrease the total chip size by 2.1%. A precise and simple model for a one-stage Fibonacci charge pump with current load is also proposed for further efficiency optimization. In a practical design, its voltage error is within 0.12% for 1 mA of current load, and it maintains a 2.83% error even for 10 mA of current load. This charge pump is fabricated through a 0.11 μm 1.5 V/6 V/32 V process, and two regulators, namely, a pulse skip one and a linear one, are operated to maintain the output of the charge pump at 30 V. The performances of the two regulators in terms of ripple, efficiency, line regulation, and load regulation are investigated.

• Journal of Korean Society of Forest Science
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• 제106권1호
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• pp.54-62
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• 2017

This study was carried to develop the chip-harvester and to analysis the operation productivity and cost for effective collection and forwarding of forest biomass. Main target specification of chip-harvester is speed of 8km/h, maximum climbing capacity of $30^{\circ}$ and maximum load capability of 2000 kg. Body structure is articulate type to reduce turning radius. Driving equipment is six-wheel drive, and a rear wheel is tandem bogie type to increase grip force. As a result of the driving test about developed chip-harvester, driving speed was 6.9 km/hr and 8.1 km/hr in ${\pm}10%$ slope with loaded and 7.3 km/hr and 7.9 km/hr in ${\pm}10%$ slope without load. As a result of the operation productivity and cost, operation productivity of grinding and forwarding was approximately $10m^3$ per day, and operation cost was 393,126 won per day.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 한국정밀공학회 2002년도 춘계학술대회 논문집
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• pp.807-811
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• 2002

As the requirements on precision and speed of motion in chip mounter increase, vibration forces are always exerted on operating conditions. To insure safety of the chip mounter, the vibration must be kept within an acceptable limit. The focus of this paper is on the identification of dynamic load characteristics and the estimation of static and dynamic stiffness characteristics for Frame Base by judicious selection of the number and the location of the support points. This study carried an analytical and experimental method to estimate the dynamic characteristics in structure.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(1)
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• pp.253-256
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• 2001

This paper describes a high speed MAC(Media Access Control) function chip for IEEE 802.11 MAC layer protocol. The MAC chip has control registers and interrupt scheme for interface with CPU and deals with transmission/reception of data as a unit of frame. The developed MAC chip is composed of protocol control block, transmission block, and reception block which supports the BCF function in IEEE 802.11 specification. The test suite which is adopted in order to verify operation of the MAC chip includes various functions, such as RTS-CTS frame exchange procedure, correct IFS(Inter Frame Space)timing, access procedure, random backoff procedure, retransmission procedure, fragmented frame transmission/reception procedure, duplicate reception frame detection, NAV(Network Allocation Vector), reception error processing, broadcast frame transmission/reception procedure, beacon frame transmission/reception procedure, and transmission/reception FIEO operation. By using this technique, it is possible to reduce the load of CPU and firmware size in high speed wireless LAN system.

• Proceedings of the KIEE Conference
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부A
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• pp.179-181
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• 1998

In this paper, one chip PWM pattern generator which eliminates time delay of computations and improves utilization factor of voltage is proposed. Both amplitude of sinusoidal signal and triangular signal are directly controlled. Thus, time delay of computations can be eliminated, and it is possible to track accurately instantaneous current for a sudden change of load with microprocessor 80C196KC. In addition, setting dead-time is also possible for wide range. From experimental work with inverter system for driving induction motor, the validity of proposed one chip PWM pattern generator is verified.

• Transactions of the Korean Society of Mechanical Engineers A
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• 제23권6호
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• pp.979-987
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• 1999

In a high precision vertical machining center, the estimation of cutting forces is important for many reasons such as prediction of chatter vibration, surface roughness and so on, and cutting forces are difficult to predict because they are very complex and time variant. In order to predict the cutting forces of end-milling process for various cutting conditions, a mathematical model is important and this model is based on chip load, cutting geometry, and the relationship between cutting forces and chip loads. Specific cutting force coefficients of the model have been obtained as interpolation function types by averaging farces of cutting tests. In this paper, the coefficients are obtained by neural network and the results of the conventional method and those of the proposed method are compared. The results show that the neural network method gives more correct values than the function type and that in teaming stage as the omitted numbers of experimental data increases the average errors increase.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 한국해양정보통신학회 2011년도 추계학술대회
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• pp.425-428
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• 2011

This paper presents a micro-scale solar energy harvesting circuit with a simple MPPT control. Solar Energy is harvested using a small off-chip PV cell generating output voltages under 0.5V instead of an on-chip PV cell. A simple MPPT is implemented using a pilot PV cell and utilizing the relationship between the open-circuit voltage of a PV cell ($V_{OC}$) and its MPP voltage ($V_{MPP}$). With applying the MPPT control, the designed circuit delivers the MPP voltage to load even though the loads is heavy such that the load circuit can operate properly. The proposed circuit is designed in TSMC 0.18um CMOS process.

• Journal of the Korean Society for Precision Engineering
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• 제14권4호
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• pp.38-45
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• 1997

A new dynamic model for the cutting process inb the end milling process is developed. This model, which describes the dynamic response of the end mill, the chip load geometry including tool runout, the dependence of the cutting forces on the chip load, is used to predict the dynamic cutting force during the end milling process. In order to predict accurately cutting forces and tool vibration, the model which uses instantaneous specific cutting force, inclueds both regenerative effect and penetration effect, The model is verified through comparisons of model predicted cutting force with measured cutting force obtained from machining experiments.