• Journal of the Microelectronics and Packaging Society
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• v.9 no.4
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• pp.47-53
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• 2002

In this study, two different (NiCuZn)-ferrite which were fabricated by using ultra-fine powders synthesized by the wet processing and conventionally commercialized powder, were investigated and compared each other in terms of the low temperature sintering and electromagnetic properties. Composition of x and w in $(Ni_{0.4-x}Cu_xZn_{0.6})_{1+w}(Fe_2O_4)_{1-w}$ were controlled as 0.2 and 0.03, respectively. The sintering temperature were $900^{\circ}C$ for ultra-fine powders by way of initial heat treatment and $1150^{\circ}C$ for commercialized powders. The (NiCuZn)-ferrite by ultra-fine powders showed love. sintering temperature than that of commercialized powders by over $200^{\circ}C$, and excellent electromagnetic properties such as the quality factor which is a important factor in the multi-layered chip inductor. In addition, characteristics of B-H hysteresis, crystallinity, microstructure and powder morphology were analyzed by a vibrating sample method(VSM), x-ray diffractometer(XRD), transmission electron microscope (TEM) and scanning electron microscope(SEM).

• Journal of the Korean Magnetics Society
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• v.13 no.3
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• pp.109-114
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• 2003

The purpose of this study Is to investigate the effect of $V_2$O$_{5}$ addition on the microstructures and magnetic properties of 7.7${\times}$4.5${\times}$1.0 mm sized multi-layer chip inductors prepared by the screen printing method using 0∼0.5 wt％ $V_2O_{5}$-doped NiCuZn ferrite pastes. With increasing the $V_2O_{5}$ content, the exaggerated grain growth of ferrite layers was developed due to the promotion of Ag diffusion and Cu segregation into the grain boundaries oi ferrites, which affected significantly the magnetic properties of the chip inductors. After sintering at $900^{\circ}C$, the inductance at 10 MHZ of the 0.5 wt％ $V_2O_{5}$-doped chip inductor was 3.7 ${\mu}$H less than 4.2 ${\mu}$H of the 0.3 wt% $V_2O_{5}$-doped one, which was thought to be caused by the residual stress at the ferrite layers increased with the promotion of Ag diffusion and Cu segregation. The quality factor of the 0.5 wt% $V_2O_{5}$-doped chip inductor decreased with increasing the sintering temperature, which was considered to be caused by the electrical resistivity of the ferrite layer decreased with the promotion of Ag/cu segregation at the grain boundaries and the growth of the mean grain size of ferrite due to exaggerated grain growth of ferrite layers.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.9 s.100
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• pp.957-963
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• 2005

This paper presents technique of wideband TIA for optical communication systems using TSMC 0.25 ${\mu}m$ CMOS RF-Mixed mode. In order to improve bandwidth characteristics of an TIA, we use active inductor shunt peaking to cascode and common-source configuration. The result shows the 37 mW and 45 mW power dissipation with 2.5 V bias and 61 dB$\Omega$ and 61.4 dB$\Omega$ transimpedance gain. And the -3 dB bandwidth of the TIA is enhanced from 0.8 GHz to 1.45 GHz in cascode and 0.61 GHz to 0.9 GHz in common-source. And the input noise current density is $5 pA/\sqrt{Hz}$ and $4.5 pA/\sqrt{Hz}$, and -10 dB out put return loss is obtained in 1.45 GHz. The total size of the chip is $1150{\times}940{\mu}m^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.17-23
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• 2003

In this study, microscale, high-performance, solenoid-type RF chip inductors were investigated. The size of the RF chip inductors fabricated in this work was 1.0${\times}$0.5${\times}$0.5㎣. The materials (96% Al2O3) and shape (I-type) of the core were determined by a Maxwell three-dimensional field simulator to maximize the performance of the inductors. The copper (Cu) wire with 40${\mu}{\textrm}{m}$ diameter was used as the coils. High frequency characteristics of the inductance (L), quality-factor (Q), and capacitance (C) of developed inductors were measured using an RF Impedance/Material Analyzer (HP4291B with HP16193A test fixture). The inductors developed have inductances of 11 to 39 nH and quality factors of 28 to 50 over the frequency ranges of 250MHz to 1 GHz, and show results comparable to those measured for the inductors prepared by CoilCraf $t^{Tm}$ that is one of the best chip inductor company in the world. The simulated data predicted the high-frequency data of the L, Q, and C of the inductors developed well.l.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.782-785
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• 2002

Power amplifier of wireless communication tranceiver can be effectually controlled output power. And small size and low power dissipation are indispensable to portable system. In this paper, to reduce the size of portable tranceiver, inductor is integrated in a single chip. And to reduce power dissipation, a power amplifier that can be digitally controlled output power, is proposed and designed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.389-393
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• 2003

This paper presents circuit modeling and characterization of silicon-based on-chip integrated inductors in Giga Hertz range for wireless communication products. We compare several different designs of on-chip inductors for self-resonant frequency and quality factor. The measurement data could be used as a design guide for manufacturing practical spiral inductors for wireless applications. We provide the equivalent inductor circuit parameters from the actual measurement data.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.283-286
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• 1999

A 2㎓, low noise, low power CMOS voltage-controlled oscillator (VCO) with an integrated LC resonator is presented. The design of VCO relies heavily on the on-chip spiral inductor. An optimized spiral inductor with Q-factor of nearly 8 is achieved and used for the VCO. The simulated result of phase noise is as low as -l14 ㏈c/Hz at an offset frequency of a 600KHz from a 2㎓ carrier frequency. The VCO is tuned with standard available junction capacitors, resulting in an about 400MHz tuning range (20%). Implemented in a five-metal 0.25${\mu}{\textrm}{m}$ standard CMOS process, the VCO consumes only 2㎽ from a single 2.5V supply. It occupies an active area of 620${\mu}{\textrm}{m}$$\times$720${\mu}{\textrm}{m}$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.6
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• pp.34-42
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• 2000

Recently, there is a growing need to develope small-size RF chip inductors operating to GHz to realize high-performance, micro-fabricated wireless communication products. For the development of high-performance RF chip inductors, however, the ferrite-based chip inductors can not be used above 300MHz due to the limitation of the permeability of this material. In this work, small-size, high-performance RF chip inductors utilizing amorphous $Al_2O_3$ core material were investigated. Copper (Cu) with 40${\mu}m$ diameter was used as the coils and the chip inductor size fabricated in this work is $2.1mm{\times}1.5mm{\times}1.0mm$. The external current source was applied after bonding Cu coil leads to gold pads electro-plated on the bottom edges of a core material. The composition of core materials was measured using a EDX. High frequency characteristics of the inductance (L), quality factor (Q), and impedance (Z) of developed inductors were measured using an RF Impedance/Material Analyzer (HP4291B with HP16193A test fixture). The developed inductors have the self-resonant frequency (SRF) of 1 to 3.5 GHz and exhibit L of 22 to 150 nH. The L of the inductors decreases with increasing the SRF. The Z of the inductors has the maximum value at the SRF and the inductors have the quality factor of 70 to 97 in the frequency range of 500 MHz to 1.5 GHz.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.1-6
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• 2017

As the performance and density of IC devices increase, especially the clock frequency increases, power grid network integrity problems become more challenging. To resolve these power integrity problems, the use of passive devices such as resistor, inductor, and capacitor is very important. To manage the power integrity with little noise or ripple, decoupling capacitors are essential in electronic packaging. The decoupling capacitors are classified into voltage regulator capacitor, board capacitor, package capacitor, and on-chip capacitor. For next generation packaging technologies such as 3D packaging or wafer level packaging on-chip MIM decoupling capacitor is the key element for power distribution and delivery management. This paper reviews the use and necessity of on-chip decoupling capacitor.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.300-312
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• 2014

A single-inductor multiple-output (SIMO) DC-DC converter providing buck and boost outputs with a new switching sequence is presented. In the proposed switching sequence, which does not require any additional blocks, input energy is delivered to outputs continuously by flowing current through the inductor, which leads to high conversion efficiency regardless of the balance between the buck and boost output loads. Furthermore, instead of multiple output loop compensation, only the freewheeling current feedback loop is compensated, which minimizes the number of off-chip components and nullifies the need for the equivalent series resistance (ESR) of the output capacitor for loop compensation. Therefore, power conversion efficiency and output voltage ripples can be improved and minimized, respectively. Implemented in a 0.35-${\mu}m$ CMOS, the proposed SIMO DC-DC converter achieves high conversion efficiency regardless of the load balance between the two outputs with maximum efficiency reaching up to 82% under heavy loads.