• Journal of the Microelectronics and Packaging Society
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• v.6 no.4
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• pp.61-71
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• 1999

The recent trend toward higher frequencies, miniaturization and lower-cost in wireless communication equipment is demanding high density packaging technologies such flip chip interconnection and multichip module(MCM) as a substitute of conventional plastic package. With analyzing the recently reported research results of the RF flip chip, this paper presents the technical issues and advantages of RF flip chip and suggest the flip chip technologies suitable for the development stage. At first, most of RF flip chips are designed in a coplanar waveguide line instead of microstrip in order to achieve better electrical performance and to avoid the interaction with a substrate. Secondly, eliminating wafer back-side grinding, via formation, and back-side metallization enables the manufacturing cost to be reduced. Finally, the electrical performance of flip chip bonding is much better than that of plastic package and the flip chip interconnection is more suitable for Transmit/Receiver modules at higher frequency. However, the characterization of CPW designed RF flip chip must be thoroughly studied and the Au stud bump bonding shall be suggested at the earlier stage of RF flip chip development.

• Journal of the Korean Society for Precision Engineering
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• v.6 no.1
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• pp.45-51
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• 1989

In metal cutting various types of chips are produced in consequence of cutting conditions. According to the type of chips the cutting mechanism is to be changed. Most of the cutting theory is based on the continuous chip because of its convenient analysis, but the occurrence of the saw-toothed chip depends upon the workpiece and/or the cutting conditions, one of which is titanium alloy used widely. Nowadays titanium alloys are used widely with the rapid development of aerospace structural engineering application, whereas the theory of cutting mechanism has not been established yet, and the formatting process has not been understood satisfactorily, either. Unfortunately several misconceptions, conflicting statements and statements needing further clarifi- cation are also found. In this paper an attempt is made to clarify the formation process of saw-toothed chips which are to be produced during the orthogonal cutting process of titanium alloys. They were machined at low speed to avoid the rapid tool wear. We observed the SEM-photographs of chips taken at the quick-st- opping device. It is hoped that a rational model of the mechanics of cyclic chip formation can be developed. The results obtained are as follows. 1. When a saw- toothed chip is formed, the shear band begins at the primary shear zone and trans- fers to the free surface, so that a segment is produced and it is completed by upsetting between the formatting segment and the formatted segment. 2. As the rake angle or the clearance angle increases in the machining of the titanium alloy, the chip approaches to that of the continous type. 3. When the rake angle and the clearance angle are increased the shear energy and the unit friction energy decrease, which shows the same aspect as that of the continuous chip.

• Proceedings of the KSME Conference
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• 2001.06d
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• pp.546-552
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• 2001

The heat transfer and flow measurements on a pedestal encountered in chip cooling. A uniform wall temperature boundary condition at the plate surface and on a pedestal was created using shroud method. Liquid crystal was used to measure the plate surface temperature. The jet Reynolds number (Re) ranges from 11,000 to 50,000, the dimensionless nozzle-to-surface distance (L/d) from 2 to 10, and the dimensionless pedestal diameter-to-height (H/D) from 0 to 1.0. The results show that the Nusselt number distributions at the near the pedestal exhibit secondary maxima at $r/d{\cong}1.0\;and\;1.5$. The formation of the secondary maxima is attributed to an create in the vortex by the pedestal.

• Journal of the Korean Society for Precision Engineering
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• v.5 no.1
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• pp.84-93
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• 1988

The on-line detection of the chip flow is one of the most important technologies in com- pletly automatic operation of machine tool, such as FMS and Unmanned Factories. This problem has been studied by many researchers, however, it is not solved as yet. For the recognition of chip flow in this study, the dynamic cutting force components due to the chip breaking were measured by dynamometer of piezo-electric type, and the frequency components of cutting force were also analyzed. From the measured results, the effect of cutting conditions and tool geometry on the dynamic cutting force component and chip formation were investigated in addition to the relationships between frequency of chip breaking (fB) and side serrated crack (fC) of chip. As a result, the following conclusions were obtaianed. 1) The chip formations have a large effect on the dynamic cutting force components. When chip breaking takes place, the dynamic cutting force component greatly increases, and the peridoic components appear, which correspond to maximum peak- frequency. 2) The crater wear of tool has a good effect on the chip control causing the chiup to be formed as upward-curl shape. In this case, the dymamic cutting force component greatly increases also 3) fB and fC of chip are closely corelated, and fC of chips has a large effect on the change of the situation of chip flow and dynamic cutting force component. 4) Under wide cutting conditions, the limit value (1.0 kgf) of dynamic cutting force component exists between the broken and continuous chips. Accordingly, this value is suitable for recognition of chip flow in on-line control of the cutting process.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.11a
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• pp.115-118
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• 2001

• Journal of Welding and Joining
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• v.24 no.2
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• pp.64-70
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• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2001.04a
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• pp.101-106
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• 2001

In order to establish the optimum process parameters and diamond saw blade composition for machining natural stone, the chip formation process and the wear process must be understood. Diamond saw blade is one of the most effective, versatile, and extensively used methods of processing rock and other hard materials, such as granite, marble, concrete and asphalt. For many years, it has been known that chip thickness is one of the most significant in the understanding of the sawing process, and other variables such as force and power have been correlated with it. In this study, mathematical relations of a material chipped by a single grit of the saw blade will be undertaken. The material chipping geometries have been mathematically defined and derived as maximum chip thickness.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1992.04a
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• pp.89-93
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• 1992

We experimented cutting characteristics-cutting force, behavior of chip, surface roughness-under low temperature, which generated by liquid nitrogen(77K). The results obtained are as follows; 1) The workpice is became to-195 .deg. C in 5, minutes, and in cooled cutting, cutting force bycooled workpices is stronger than normal temperature condition. Chip thickness is decreasing comparative toN.C and shear angle in shear plane is in creasing. 2) Chip formation becomes long or short tubular chips in turning SXM440, SNCM21 steel, when cutting speed is low and cutting temperatre is cooled condition, but in the STS304 steel the variation of c formations isn't known to. 3) In C.C, surface roughness of workpices is better than N.C and found to make more the crat wearthan N.C 4) It is possible to detect the behavior of chip by monitoring the maximum amplitude of gai value of cutting force.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.8 no.4
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• pp.14-19
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• 2009

Micro fluid channels are machined on quartz glass using powder blasting, and the machining characteristics of the channels are experimentally evaluated. The powder blasting process parameters such as injection pressure, abrasive particle size and density, stand-off distance, number of nozzle scanning, and shape/size of the required patterns affect machining results. In this study, the influence of the number of nozzle scanning, abrasive particle size, and blasting pressure on the formation of micro channels is investigated. Machined shapes and surface roughness are measured, and the results are discussed. Through the experiments and analysis, LOC are ettectinely machined on quartz glass using powder blasting.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.4
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• pp.81-86
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• 2003

Electromigration of Sn-3.5Ag solder bump was investigated using flip chip specimens which consisted of upper Si chip and lower Si substrate. While the resistance of the flip chip sample did not almost change until the time right before the failure, the resistivity increased abruptly at the moment when complete failure of the solder joint occurred in the flip chip sample. At current densities of $3\times 10^4$∼$4\times 10^4$A/$\textrm{cm}^2$, the activation energy for electromigration of the Sn-3.5Ag solder bump was characterized as ∼0.7 eV. Failure of the Sn-3.5Ag solder bump occurred at the solder/UBM interface due to the formation and propagation of voids at cathode side of the solder bump.