• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.1176-1178
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• 1992

This paper shows enhanced working performance of the battery fork-lift truck by developing the IGBT full bridge dc-dc convertor using one-chip micro-processor. The PWM pulse is generated from a 16 bit one-chip micro-processor for the speed control of DC motor. In order to ensure the operation of IGBT and motor pecewisely, IGBT gate drive circuit was designed by using current limiting IC and hige voltage limit IC. And also It is able to regenerative braking.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.13 no.4
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• pp.30-36
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• 2004

The development of LD(Laser Diode) tester and its control system based on the graphical programming language(LabVIEW) is addressed. The ill tester is used to check the optic power and the optic spectrum of the LD Chip. The emitter size of LD chip and the diameter of the Detector(optic fiber and photo diode) are very small, therefore the test device needs high accuracy. But each motion part of the test device could not accomplish high accuracy due to the limit of the mechanical performance. So, an image processing with machine vision is proposed to compensate for the error. By adopting our method we can reduce the error of position within $\pm$5$\mu\textrm{m}$.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.8
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• pp.995-1000
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• 1999

This paper presents a optic system and a visual inspection algorithm looking for solder joint defects of J-lead chip which are more integrate and smaller than ones with Gull-wing on PCBs(Printed Circuit Boards). The visual inspection system is composed of three sections : host PC, imaging and driving parts. The host PC part controls the inspection devices and executes the inspection algorithm. The imaging part acquires and processes image data. And the driving part controls XY-table for automatic inspection. In this paper, the most important five features are extracted from input images to categorize four classes of solder joint defects in the case of J-lead chip and utilized to a back-propagation network for classification. Consequently, good accuracy of classification performance and effectiveness of chosen five features are examined by experiment using proposed inspection algorithm.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1098-1100
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• 2005

The floorplanning problem is an essential design step in VLSI layout design and it is how to place rectangular modules as density as possible. And then, as the DSM advances, the VLSI chip becomes more congested even though more metal layers are used for routing. Usually, a VLSI chip includes several buses. As design increases in complexity, bus routing becomes a heavy task. To ease bus routing and avoid unnecessary iterations in physical design, we need to consider bus planning in early floorplanning stage. In this paper, we propose a floorplanning method for topological constraint consisting of bus constraint and memory constraint. The proposed algorithms based on Genetic Algorithm(GA) is adopted a sequence pair. For selection control, new objective functions are introduced for topological constraint. Studies on floor planning and cell placement have been reported as being applications of GA to the LSI layout problem. However, no studies have ever seen the effect of applying GA in consideration of topological constraint. Experimental results show improvement of bus and memory constraint.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.12
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• pp.1644-1651
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• 1995

A data and clock recovery integrated circuit for MAC (Multiplexed Analog Component) TV standard is described. The chip performs the recovery of a system clock from a digitally encoded voice signal, clamping of a video signal for DC-level restoration, and precise gain control of a video signal in the presence of a large amplitude variation. A PLL (Phase Locked Loop) is used for timing recovery and a new gain control circuit is proposed which enhances its accuracy and dynamic range by employing two identical four-quadrant analog multipliers. The chip is designed in full custom with 1.5um BiCMOS technology, and layout verification is completed by post-simulation with the extracted circuit.

• Journal of the Korean Society for Precision Engineering
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• v.18 no.11
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• pp.161-167
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• 2001

In this study, the control of mounting system for MLGA package was developed using machine vision for the control of rotation position compensation and mounting position of X-Y table. Two types of materials, polymer and alumina, were used for the dielectric insulator of the MLGA. The illumination system and the algorithm of position compensation which is suitable for these materials was developed. We found that the mounting accuracy enough to the degree of${\pm}10{\mu}m$ when MLGA was mounted on the PCB.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.988-990
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• 2000

This paper presents the software control of a brush-less DC motor. Not only speed and current controls but also a real-time identification of the motor parameters can be implemented by software using the digital signal processor (DSP) TMS320F240. The DSP Controller TMS320F240 from Texas Instruments is suitable for a wide range of motor drives. TMS320F240 provides a single chip solution by integrating on-chip not only a high computational power but also all the peripherals necessary for electric motor control. The main benefits are increased system reliability and cost reduction of the overall system. The present paper describes how a speed controlled brushless DC drive can be implemented using TMS320F240.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.319-325
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• 2015

This paper presents an efficient vibration energy harvester with a piezoelectric (PE) cantilever. The proposed PE energy harvester increases the efficiency through minimization of hardware complexity and hence reduction of power dissipation of the circuit. Two key features of the proposed energy harvester are (i) incorporation synchronized switches with a simple control circuit, and (ii) a feed-forward buck converter with a simple control circuit. The chip was fabricated in $0.18{\mu}m$ CMOS processing technology, and the measured results indicate that the proposed rectifier achieves the efficiency of 77%. The core area of the chip is 0.2 mm2.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.11
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• pp.1641-1646
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• 2013

Control voltage for baseband channel selection filter to select one of communication channels can be easily fluctuated according to external noise or variation of fabrication. In this paper, we design a voltage regulator with small chip area to keep control voltage constantly using current comparative method. Cut-off frequency of channel selection filter is automatically controlled by detecting current flow using the proposed voltage regulator.

• Proceedings of the KIEE Conference
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• 1995.07a
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• pp.318-320
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• 1995

This paper describes the practical implementation of switched reluctance motor drive for a wide range of operation speeds. The angle controller is designed by one-chip microprocessor 8051 for various real time applications. Algorithm to control the speed of SRM and to maintain the speed under the changed load is proposed.