• Title/Summary/Keyword: Chip assembly

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The Low Height Looping Technology for Multi-chip Package in Wire Bonder (와이어 본더에서의 초저 루프 기술)

  • Kwak, Byung-Kil;Park, Young-Min;Kook, Sung-June
    • Journal of the Semiconductor & Display Technology
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    • v.6 no.1 s.18
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    • pp.17-22
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    • 2007
  • Recent new packages such as MCP(Multi-Chip Package), QDP(Quadratic Die Package) and DDP(Dual Die Package) have stack type configuration. This kind of multi-layer package is thicker than single layer package. So there is need for the low height looping technology in wirebonder to make these packages thinner. There is stiff zone above ball in wirebonder wire which is called HAZ(Heat Affect Zone). When making low height loop (below $80\;{\mu}m$) with traditional forward loop, stiff wire in HAZ(Heat Affected Zone) above ball is bended and weakened. So the traditional forward looping method cannot be applied to low height loop. SSB(stand-off stitch) wire bonding method was applied to many packages which require very low loops. The drawback of SSB method is making frequent errors at making ball, neck damage above ball on lead and the weakness of ball bonding on lead. The alternative looping method is BNL(ball neckless) looping technology which is already applied to some package(DDP, QDP). The advantage of this method is faster in bonding process and making little errors in wire bonding compared with SSB method. This paper presents the result of BNL looping technology applied in assembly house and several issues related to low loop height consistence and BNL zone weakness.

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Implementation and Verification of JPEG Decoder IP using a Virtual Platform (가상 플랫폼을 이용한 JPEG 디코더 IP의 구현 및 검증)

  • Jung, Yong-Bum;Kim, Yong-Min;Hwang, Chul-Hee;Kim, Jong-Myon
    • Journal of the Korea Society of Computer and Information
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    • v.16 no.11
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    • pp.1-8
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    • 2011
  • The requirement of a system-on-a-chip (SoC) design is increasing, which combines various and complex functional units on a single device. However, short time to market prohibits to release the device. To satisfy this shorter time-to-market, verification of both hardware and software at the same time is important. A virtual platform-based design method supports faster verification of these combined software and hardware by reusing pre-defined intellectual properties (IP). In this paper, we introduce the virtual platform-based design and redesign the existing ARM processor based S3C2440A system using the virtual platform-based method. In addtion, we implement and evaluate the performance of a JPEG decoder on the S3C2440A virtual platform. Furthermore, we introduce an optimized technique of the JPEG decoder using the ARM based inline assembly language, and then verify the performance improvement on the virtual platform. Such virtual platform-based design allows to verify both software and hardware at the same time and can meet the requirement of the shorter time-to-market.

Low-Power Implementation of A Multichannel Hearing Aid Using A General-purpose DSP Chip (범용 DSP 칩을 이용한 다중 채널 보청기의 저전력 구현)

  • Kim, Bum-Jun;Byun, Joon;Park, Young-Cheol
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.11 no.1
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    • pp.18-25
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    • 2018
  • In this paper, we present a low-power implementation of the multi-channel hearing aid system using a general-purpose DSP chip. The system includes an acoustic amplification algorithm based on Wide Dynamic Range Compression (WDRC), an adaptive howling canceller, and a single-channel noise reduction algorithm. To achieve a low-power implementation, each algorithm is re-constructed in forms of integer program, and the integer program is converted to the assembly program using BelaSigna(R) 250 instructions. Through experiments using the implementation system, the performance of each processing algorithm was confirmed in real-time. Also, the clock of the implementation system was measured, and it was confirmed that the entire signal processing blocks can be performed in real time at about 7.02MHz system clock.

3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

  • Lee, Kang-Wook
    • Journal of the Microelectronics and Packaging Society
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    • v.22 no.2
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    • pp.11-19
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    • 2015
  • Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

Cost Effective Silica-Based 100 G DP-QPSK Coherent Receiver

  • Lee, Seo-Young;Han, Young-Tak;Kim, Jong-Hoi;Joung, Hyun-Do;Choe, Joong-Seon;Youn, Chun-Ju;Ko, Young-Ho;Kwon, Yong-Hwan
    • ETRI Journal
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    • v.38 no.5
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    • pp.981-987
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    • 2016
  • We present a cost-effective dual polarization quadrature phase-shift coherent receiver module using a silica planar lightwave circuit (PLC) hybrid assembly. Two polarization beam splitters and two $90^{\circ}$ optical hybrids are monolithically integrated in one silica PLC chip with an index contrast of $2%-{\Delta}$. Two four-channel spot-size converter integrated waveguide-photodetector (PD) arrays are bonded on PD carriers for transverse-electric/transverse-magnetic polarization, and butt-coupled to a polished facet of the PLC using a simple chip-to-chip bonding method. Instead of a ceramic sub-mount, a low-cost printed circuit board is applied in the module. A stepped CuW block is used to dissipate the heat generated from trans-impedance amplifiers and to vertically align RF transmission lines. The fabricated coherent receiver shows a 3-dB bandwidth of 26 GHz and a common mode rejection ratio of 16 dB at 22 GHz for a local oscillator optical input. A bit error rate of $8.3{\times}10^{-11}$ is achieved at a 112-Gbps back-to-back transmission with off-line digital signal processing.

Linear and Circular Interpolation for 2-Dimensional Contouring Control (2次元 輪곽制御 를 위한 直線 및 圓통補間)

  • 이봉진
    • Transactions of the Korean Society of Mechanical Engineers
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    • v.6 no.4
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    • pp.341-345
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    • 1982
  • The interpolator is usually built in hardware (logic circuitry), and the interpolator fabricated in a single LSI chip is recently made use of in most NC controllers, making the system more compact. However, the LSI interpolator not only has the technical difficulties but also requires high cost, in its fabrication. To solve these problems, we tried to find the method of interpolation by software, and succeeded in developing a program which, executed by INTEL's 8085 microprocessor, can distribute the input pulses of up to 4.0 [Kpps] for the linear interpolation and 3.0 [Kpps] for the circular interpolation. This paper presents the algorithm used to reduce the execution time and the flow chart of the interpolation program, and also shows the possibility of software interpolation. The interpolation program designed in assembly language is presented in the appendix.

Leadframe Feeder Heat Rail Design and Verification (Leadframe Feeder Heat Rail의 설계와 검증)

  • Kim, Won-Jong;Hwang, Eun-Ha
    • Journal of the Korean Society of Industry Convergence
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    • v.15 no.1
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    • pp.37-42
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    • 2012
  • Trends in semiconductor equipment industry are to reduce the cost of producing semiconductor, semiconductor process development, facility development, and the minimum investment in terms of cost and quality. Semiconductor equipments are being considered to review and development is proceeding at the same time. In the first part of the semiconductor assembly process, in which the importance of die bonding process is emerging, a wide leadframe type die bonding machine is demanded for productivity. Die bonding machine was designed through experiments and by trial and error. It costs a lot of time and financial burden. The purpose of this study is to solve these problems by using the CAE tool 3G. By using finite element method, thermal analysis of die bonding machine to the various widths leadframe die bonder machine rail is performed for design.

A Study on the Multistage Screening Procedure when Inspection Errors are Present (검사 오류를 고려한 다단계 선별절차에 관한 연구)

  • Kwon, Hyuck-Moo;Kim, Young-Jin
    • Journal of Korean Society for Quality Management
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    • v.33 no.4
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    • pp.88-95
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    • 2005
  • Multistage screening is a common practice when a component has a critical effect on the function of the assembly. A defect in a component might incur malfunction of an electronic device, resulting in a great amount of loss. Multistage screening, including duplicated screening inspections, may provide a good solution for this problem when inspection errors are present. In the company studied here, the manufacturing process of the multiple layer chip capacitor includes two-stage screening. In the first stage, screening inspection is performed repeatedly until no defects are found in the lot. In the second stage, sampling inspection is performed by a group of experts prior to shipment. In this article, we review the procedure used in the field and suggest a revised model of the multiple screening procedure and solution method for this situation. The usefulness of the proposed model is discussed through a practical example.

Surface Analysis of Aluminum Bonding Pads in Flash Memory Multichip Packaging

  • Son, Dong Ju;Hong, Sang Jeen
    • Transactions on Electrical and Electronic Materials
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    • v.15 no.4
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    • pp.221-225
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    • 2014
  • Although gold wire bonding techniques have already matured in semiconductor manufacturing, weakly bonded wires in semiconductor chip assembly can jeopardize the reliability of the final product. In this paper, weakly bonded or failed aluminum bonding pads are analyzed using X-ray photoelectron spectroscopy (XPS), Auger electron Spectroscopy (AES), and energy dispersive X-ray analysis (EDX) to investigate potential contaminants on the bond pad. We found the source of contaminants is related to the dry etching process in the previous manufacturing step, and fluorocarbon plasma etching of a passivation layer showed meaningful evidence of the formation of fluorinated by-products of $AlF_x$ on the bond pads. Surface analysis of the contaminated aluminum layer revealed the presence of fluorinated compounds $AlOF_x$, $Al(OF)_x$, $Al(OH)_x$, and $CF_x$.

Epoxy solder paste and its applications (에폭시 솔더 페이스트 소재와 적용)

  • Moon, Jong-Tae;Eom, Yong-Sung;Lee, Jong-Hyun
    • Journal of Welding and Joining
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    • v.33 no.3
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    • pp.32-39
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    • 2015
  • With the simplicity of process and high reliability in chip or package bonding, epoxy solder paste (ESP) has been recently considered as a competitive bonding material. The ESP material is composed of solder powder and epoxy formulation which can remove oxide layers on the surface of solder powder and pad finish metal. The bonding formed using ESP shows outstanding bonding strength and suppresses electrical short between adjacent pads or leads owing to the reinforced structure by cured epoxy after the bonding. ESP is also expected to suppress the formation and growth of whisker on the pads or leads. With the mentioned advantages, ESP is anticipated to become a spotlighted bonding material in the assembly of flexible electronics and electronic modules in automotive vehicles.