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http://dx.doi.org/10.9708/jksci.2011.16.11.001

Implementation and Verification of JPEG Decoder IP using a Virtual Platform  

Jung, Yong-Bum (School of Electrical Engineering, University of Ulsan)
Kim, Yong-Min (School of Electrical Engineering, University of Ulsan)
Hwang, Chul-Hee (School of Electrical Engineering, University of Ulsan)
Kim, Jong-Myon (School of Electrical Engineering, University of Ulsan)
Publication Information
Journal of the Korea Society of Computer and Information / v.16, no.11, 2011 , pp. 1-8 More about this Journal
Abstract
The requirement of a system-on-a-chip (SoC) design is increasing, which combines various and complex functional units on a single device. However, short time to market prohibits to release the device. To satisfy this shorter time-to-market, verification of both hardware and software at the same time is important. A virtual platform-based design method supports faster verification of these combined software and hardware by reusing pre-defined intellectual properties (IP). In this paper, we introduce the virtual platform-based design and redesign the existing ARM processor based S3C2440A system using the virtual platform-based method. In addtion, we implement and evaluate the performance of a JPEG decoder on the S3C2440A virtual platform. Furthermore, we introduce an optimized technique of the JPEG decoder using the ARM based inline assembly language, and then verify the performance improvement on the virtual platform. Such virtual platform-based design allows to verify both software and hardware at the same time and can meet the requirement of the shorter time-to-market.
Keywords
Virtual platform; system on a chip; JPEG decoder; inline assembly;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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