• Title/Summary/Keyword: Chip Scale Package (CSP)

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BGA to CSP to Flip Chip-Manufacturing Issues

  • Caswell, Greg;Partridge, Julian
    • Journal of the Microelectronics and Packaging Society
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    • v.8 no.2
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    • pp.37-42
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    • 2001
  • The BGA package has been the area array package of choice for several years. Recently, the transition has been to finer pitch configurations called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch. requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and place equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

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BGA to CSP to Flip Chip - Manufacturing Issues

  • Caswell, Greg;Partridge, Julian
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2001.04a
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    • pp.27-34
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    • 2001
  • The BGA Package has been the area array package of choice for several rears. Recently, the transition has been to finer pitch configuration called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch, requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and piece equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

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Characteristics of Lead Frame Chip Scale Package(LF-CSP)

  • Hong, Sung-Hak
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 1999.12a
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    • pp.63-85
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    • 1999
  • $\cdot$New CSP using Lead Frame and solder ball techniques. $\cdot$EMC needs high filler content, low CTE and high flexural modulus. $\cdot$Solder Joint Reliability improved by anchor leads. .Uniform inner lead shape would be better at capacitance values. $\cdot$Low Assembly cost CSP.

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Underfill Technology (언더필 기술)

    • Journal of the Korean institute of surface engineering
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    • v.36 no.2
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    • pp.214-225
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    • 2003
  • Trends in microelectronics packages such as low cost, miniaturization, high performance, and high reliability made area array interconnecting technologies including flip chip, CSP (Chip Scale Package) and BGA (Ball Grid Array) mainstream technologies. Underfill technology is used for the reliability of the area array technologies, thus electronics packaging industry regards it as very important technology In this paper, the underfill technology is reviewed and the recent advances in the underfill technology including new processes and materials are introduced. These includes reworkable underfills, no-flow underfills, molded underfills and wafer - level - applied underfills.

The Moisture Absorption Properties of Liquid Type Epoxy Molding Compound for Chip Scale Package According to the Change of Fillers (충전재 변화에 따른 Chip Scale Package(CSP)용 액상 에폭시 수지 성형물 (Epoxy Molding Compound)의 흡습특성)

  • Kim, Whan-Gun
    • Journal of the Korean Chemical Society
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    • v.54 no.5
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    • pp.594-602
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    • 2010
  • Since the requirement of the high density integration and thin package technique of semiconductor have been increasing, the main package type of semiconductor will be a chip scale package (CSP). The changes of diffusion coefficient and moisture content ratio of epoxy resin systems according to the change of liquid type epoxy resin and fillers for CSP applications were investigated. The epoxy resins used in this study are RE-304S, RE310S, and HP-4032D, and Kayahard MCD as hardener and 2-methylimidazole as catalyst were used in these epoxy resin systems. The micro-sized and nano-sized spherical type fused silica as filler were used in order to study the moisture absorption properties of these epoxy molding compound (EMC) according to the change of filler size. The temperature of glass transition (Tg) of these EMC was measured using Dynamic Scanning Calorimeter (DSC), and the moisture absorption properties of these EMC according to the change of time were observed at $85^{\circ}C$ and 85% relative humidity condition using a thermo-hygrostat. The diffusion coefficients in these EMC were calculated in terms of modified Crank equation based on Ficks' law. An increase of diffusion coefficient and maximum moisture absorption ratio with Tg in these systems without filler can be observed, which are attributed to the increase of free volume with Tg. In the EMC with filler, the changes of Tg and maximum moisture absorption ratio with the filler content can be hardly observed, however, the diffusion coefficients of these systems with filler content show the outstanding changes according to the filler size. The diffusion via free volume is dominant in the EMC with micro-sized filler; however, the diffusion with the interaction of absorption according the increase of the filler surface area is dominant in the EMC with nano-sized filler.

A study on electrical characteristics fo high speed bottom leaded plastic(BLP) package (고속 bottom leaded plastic(BLP) package의 전기적 특성에 관한 연구)

  • 신명진;유영갑
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.35D no.4
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    • pp.61-70
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    • 1998
  • The electrical performance of a package is extremely important for high speed digital system operations. CSP(chip scale package) is known to have better electrical performance than the convnetional packages. In this paper, the electrical performance of the BLP(bottom leaded plastic) package, a kind of CSP, has been alayzed by both simulation and real measurement. The electrical perfdormance of a BLP was compared with that of the conventioanl TSOP(thin small outline package). The leadinductanceand lead capacitance were used for the comparison purposes. The new BLP design provides much better electrical performance that TSOP package. It has about 40% favorable parameter values.

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Development of Seesaw-Type CSP Solder Ball Loader (CSP용 시소타입 로딩장치의 개발)

  • Lee, J.H.;Koo, H.M.;Woo, Y.H.;Lee, C.W.;Shin, Y.E.
    • Proceedings of the KSME Conference
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    • 2000.04a
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    • pp.873-878
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    • 2000
  • Semiconductor packaging technology is changed rapidly according to the trends of the micro miniaturization of multimedia and information equipment. For I/O limitation and fine pitch limitation, DIP and SOP/QFP are replaced by BGA/CSP. This is one of the surface mount technology(SMT). Solder ball is bumped n the die pad and connected onto mounting board. In ball bump formation, vacuum suction type ball alignment process is widely used, However this type has some problems such as ionization, static electricity and difficulty of fifo(first-input first-out) of solder balls. Seesaw type is reducing these problems and has a structural simplicity and economic efficiency. Ball cartridge velocity and ball aligned plate angle are Important variables to improve the ball alignment Process. In this paper, seesaw-type CSP solder ball loader is developed and the optimal velocity and plate angle are proposed.

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A Wafer Level Packaged Limiting Amplifier for 10Gbps Optical Transmission System

  • Ju, Chul-Won;Min, Byoung-Gue;Kim, Seong-Il;Lee, Kyung-Ho;Lee, Jong-Min;Kang, Young-Il
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.4 no.3
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    • pp.189-195
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    • 2004
  • A 10 Gb/s limiting amplifier IC with the emitter area of $1.5{\times}10{\mu}m^2$ for optical transmission system was designed and fabricated with a AIGaAs/GaAs HBTs technology. In this stud)', we evaluated fine pitch bump using WL-CSP (Wafer Level-Chip Scale Packaging) instead of conventional wire bonding for interconnection. For this we developed WL-CSP process and formed fine pitch solder bump with the $40{\mu}m$ diameter and $100{\mu}m$ pitch on bonding pad. To study the effect of WL-CSP, electrical performance was measured and analyzed in wafer and package module using WL-CSP. In a package module, clear and wide eye diagram openings were observed and the riselfall times were about 100ps, and the output" oltage swing was limited to $600mV_{p-p}$ with input voltage ranging from 50 to 500m V. The Small signal gains in wafer and package module were 15.56dB and 14.99dB respectively. It was found that the difference of small signal gain in wafer and package module was less then 0.57dB up to 10GHz and the characteristics of return loss was improved by 5dB in package module. This is due to the short interconnection length by WL-CSP. So, WL-CSP process can be used for millimeter wave GaAs MMIC with the fine pitch pad.