• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2008년도 춘계학술대회 논문집
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• pp.15-16
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• 2008

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2011년도 춘계학술대회 논문집
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• pp.821-822
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• 2011

• 마이크로전자및패키징학회지
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• 제8권2호
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• pp.37-42
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• 2001

The BGA package has been the area array package of choice for several years. Recently, the transition has been to finer pitch configurations called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch. requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and place equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 Proceedings of 6th International Joint Symposium on Microeletronics and Packaging
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• pp.27-34
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• 2001

The BGA Package has been the area array package of choice for several rears. Recently, the transition has been to finer pitch configuration called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch, requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and piece equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 1999년도 1st Korea-Japan Advanced Semiconductor Packaging Technology Seminar
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• pp.63-85
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• 1999

$\cdot$New CSP using Lead Frame and solder ball techniques. $\cdot$EMC needs high filler content, low CTE and high flexural modulus. $\cdot$Solder Joint Reliability improved by anchor leads. .Uniform inner lead shape would be better at capacitance values. $\cdot$Low Assembly cost CSP.

• 한국표면공학회지
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• 제36권2호
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• pp.214-225
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• 2003

Trends in microelectronics packages such as low cost, miniaturization, high performance, and high reliability made area array interconnecting technologies including flip chip, CSP (Chip Scale Package) and BGA (Ball Grid Array) mainstream technologies. Underfill technology is used for the reliability of the area array technologies, thus electronics packaging industry regards it as very important technology In this paper, the underfill technology is reviewed and the recent advances in the underfill technology including new processes and materials are introduced. These includes reworkable underfills, no-flow underfills, molded underfills and wafer - level - applied underfills.

• 대한화학회지
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• 제54권5호
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• pp.594-602
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• 2010

반도체의 경박단소화, 고밀도화에 따라 향후 반도체 패키지의 주 형태는 CSP(Chip Scale Package)가 될 것이다. 이러한 CSP에 사용되는 에폭시 수지 시스템의 흡습특성을 조사하기 위하여 에폭시 수지 및 충전재 변화에 따른 확산계수와 흡습율 변화를 조사하였다. 본 연구에 사용된 에폭시 수지로는 RE-304S, RE-310S, 및 HP-4032D를, 경화제로는 Kayahard MCD를, 경화촉매로는 2-methyl imidazole을 사용하였다. 충전재 크기 변화에 따른 에폭시 수지 성형물의 흡습특성을 조사하기 위하여 충전재로는 마이크로 크기 수준 및 나노 크기 수준의 구형 용융 실리카를 사용하였다. 이러한 에폭시 수지 성형물의 유리전이온도는 시차주사열량계를 이용하여 측정하였으며, 시간에 따른 흡습특성은 $85^{\circ}C$ and 85% 상대습도 조건하에서 항온항습기를 사용하여 측정하였다. 에폭시 수지 성형물의 확산계수는 Ficks의 법칙에 기초한 변형된 Crank 방정식을 사용하여 계산 하였다. 충전재를 사용하지 않은 에폭시 수지 시스템의 경우, 유리전이온도가 증가함에 따라 확산계수와 포화흡습율이 증가 하였으며 이는 유리전이온도 증가에 따른 에폭시 수지 성형물의 자유부피 증가로 설명하였다. 충전재를 사용한 경우, 충전재의 함량 증가에 따라 유리전이온도와 포화흡습율은 거의 변화가 없었으나, 확산계수는 충전재의 입자 크기에 따라 많은 변화를 보여주었다. 마이크로 크기 수준의 충전재를 사용한 경우 확산은 자유부피를 통하여 주로 이루어지나, 나노 크기 수준의 충전재를 사용한 에폭시 수지 성형물에서는 충전재의 표면적 증가에 따른, 수분 흡착의 상호작용을 통한 확산이 지배적으로 이루어진다고 판단된다.

• 전자공학회논문지D
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• 제35D권4호
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• pp.61-70
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• 1998

The electrical performance of a package is extremely important for high speed digital system operations. CSP(chip scale package) is known to have better electrical performance than the convnetional packages. In this paper, the electrical performance of the BLP(bottom leaded plastic) package, a kind of CSP, has been alayzed by both simulation and real measurement. The electrical perfdormance of a BLP was compared with that of the conventioanl TSOP(thin small outline package). The leadinductanceand lead capacitance were used for the comparison purposes. The new BLP design provides much better electrical performance that TSOP package. It has about 40% favorable parameter values.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2000년도 춘계학술대회논문집A
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• pp.873-878
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• 2000

Semiconductor packaging technology is changed rapidly according to the trends of the micro miniaturization of multimedia and information equipment. For I/O limitation and fine pitch limitation, DIP and SOP/QFP are replaced by BGA/CSP. This is one of the surface mount technology(SMT). Solder ball is bumped n the die pad and connected onto mounting board. In ball bump formation, vacuum suction type ball alignment process is widely used, However this type has some problems such as ionization, static electricity and difficulty of fifo(first-input first-out) of solder balls. Seesaw type is reducing these problems and has a structural simplicity and economic efficiency. Ball cartridge velocity and ball aligned plate angle are Important variables to improve the ball alignment Process. In this paper, seesaw-type CSP solder ball loader is developed and the optimal velocity and plate angle are proposed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.189-195
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• 2004

A 10 Gb/s limiting amplifier IC with the emitter area of $1.5{\times}10{\mu}m^2$ for optical transmission system was designed and fabricated with a AIGaAs/GaAs HBTs technology. In this stud)', we evaluated fine pitch bump using WL-CSP (Wafer Level-Chip Scale Packaging) instead of conventional wire bonding for interconnection. For this we developed WL-CSP process and formed fine pitch solder bump with the $40{\mu}m$ diameter and $100{\mu}m$ pitch on bonding pad. To study the effect of WL-CSP, electrical performance was measured and analyzed in wafer and package module using WL-CSP. In a package module, clear and wide eye diagram openings were observed and the riselfall times were about 100ps, and the output" oltage swing was limited to $600mV_{p-p}$ with input voltage ranging from 50 to 500m V. The Small signal gains in wafer and package module were 15.56dB and 14.99dB respectively. It was found that the difference of small signal gain in wafer and package module was less then 0.57dB up to 10GHz and the characteristics of return loss was improved by 5dB in package module. This is due to the short interconnection length by WL-CSP. So, WL-CSP process can be used for millimeter wave GaAs MMIC with the fine pitch pad.