• The Journal of Information Systems
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• v.20 no.3
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• pp.111-127
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• 2011

This study is intended for international cooperation in the field of LED were analyzed. The results, LED wide coverage areas, and a promising future is expected to grow fast enough to occupancy for a major national technology is a competitive situation. Chip Scale Package, including our country, such as LED manufacturing technology that might be competitive in parts, but new technologies such as renal substrate R&D and technology development still active preemption is not the situation. Renal substrate, particularly, large-diameter sapphire, large size/large LED manufacturers, such as a promising area for future research and development support will be needed. To do this, previous research in this area and the U.S., Japan cooperation in such studies also will need to expand. Bibliometrics way through this study, analytical techniques and analytical tools used in the integrated analysis of the usefulness and necessity of the system development were found.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.86.3-86
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• 2001

Hall effect sensor using 7um, 1.7 ohm-cm or 10um, 3.5 ohm-cm Bipolar process was successfully developed. The Hall sensor consists of various patterns, such as regular shapes, rectangles, diamond, hexagon and cross shapes to optimize offset voltage and sensitivity for proper applications. In order to measure offset voltage in chip scale the Agilent company´s 4156C and Nano-Voltage Meter were used and the best structure in offset voltage was finally selected by using ceramic package. The patterns appear to be the quadri-rectangular patterns entirely and three-parallelogram patterns. The measured offset voltages were found to be about 173-365uV. Meanwhile, in ...

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2005.09a
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• pp.67-88
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• 2005

Mold-Flow 3 Die Stack CSP of Mold array packaging with different Gate types. As high density package option such as 3 or 4 die stacking technologies are developed, the major concerning points of mold related qualities such as incomplete mold, exposed wires and wire sweeping issues are increased because of its narrow space between die top and mold surface and higher wiring density. Full 3D rheokinetic simulation of Mold flow for 3 die stacking structure case was done with the rheological parameters acquired from Slit-Die rheometer and DSC of commercial EMC. The center gate showed severe void but corner gate showed relatively better void performance. But in case of wire sweeping related, the center gate type showed less wire sweeping than corner gate types. From the simulation results, corner gate types showed increased velocity, shear stress and mold pressure near the gate and final filling zone. The experimental Case study and the Mold flow simulation showed good agreement on the mold void and wire sweeping related prediction. Full 3D simulation methodologies with proper rheokinetic material characterization by thermal and rheological instruments enable the prediction of micro-scale mold filling behavior in the multi die stacking and other complicated packaging structures for the future application.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.4
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• pp.503-509
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• 2019

The demand for smaller, faster, and multi-functional mobile devices in increasing at a rapidly increasing rate. In response to these trends, Stacked Chip Scale Package (SCSP) is used widely in the assembly industry. A film type adhesive called die attach film (DAF) is used widely for bonding chips in SCSP. The DAF requires high flowability at high die attachment temperatures for bonding chips on organic substrates, where the DAF needs to feel the gap depth, or for bonding the same sized dies, where the DAF needs to penetrate bonding wires. In this study, the mixture design of experiment (DOE) was performed for three raw materials to obtain the optimized DAF recipe for low elastic modulus at high temperature. Three components are acrylic polymer (SG-P3) and two solid epoxy resins (YD011 and YDCN500-1P) with different softening points. According to the DOE results, the elastic modulus at high temperature was influenced greatly by SG-P3. The elastic modulus at $100^{\circ}C$ decreased from 1.0 MPa to 0.2 MPa as the amount of SG-P3 was decreased by 20%. In contrast, the elastic modulus at room temperature was dominated by YD011, an epoxy with a higher softening point. The optimized DAF recipe showed approximately 98.4% pickup performance when a UV dicing tape was used. A DAF crack that occurred in curing was effectively suppressed through optimization of the cure accelerator amount and two-step cure schedule. The imizadole type accelerator showed better performance than the amine type accelerator.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.12
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• pp.261-267
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• 2020

The demand for faster, lighter, and thinner portable electronic devices has brought about a change in semiconductor packaging technology. In response, a stacked chip-scale package(SCSP) is used widely in the assembly industry. One of the key materials for SCSP is a die-attach film (DAF). Excellent flowability is needed for DAF for successful die attachment without voids. For DAF with high flowability, two-step curing is often required to reduce a cure crack, but one-step curing is needed to reduce the processing time. In this study, DAF composition was categorized into three groups: cure (epoxy resins), soft (rubbers), hard (phenoxy resin, silica) component. The effect of the composition on a cure crack was examined when one-step curing was applied. The die-attach void and flowability were also assessed. The cure crack decreased as the amount of hard components decreased. Die-attach voids also decreased as the amount of hard components decreased. Moreover, the decrease in cure component became important when the amount of hard component was small. The flowability was evaluated using high-temperature storage modulus and bleed-out. A decrease in the amount of hard components was critical for the low storage modulus at 100℃. An increase in cure component and a decrease in hard component were important for the high bleed-out at 120℃(BL-120).

• Journal of the Microelectronics and Packaging Society
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• v.9 no.4
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• pp.61-68
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• 2002

Thermal shock testing was used to evaluate reliability that appeared in the solder joints of electronic devices when they were subjected to thermal cycling. Recently, mobile devices have come smaller and multi-functional, with the increasing need for high-density packaging, BGA or CSP has become the main trend for surface mounting technology, and therefore mechanical stress life for solder joints in BGA/CSP type packages has required. Reliability of BGA/CSP solder joints was evaluated with electric resistivity change of daisy chain pattern and stress-strain curve measured using strain gage attached on the surface of PCB under mechanical impact loading. In this report, applications of PCB Universal Testing Machine we have developed and experimental datum of SONY estimating dynamic behavior of mechanical stress in BGA/CSP solder joints are introduced.

• Smart Structures and Systems
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• v.6 no.5_6
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• pp.661-673
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• 2010

This paper presents recent developments in an extremely compact, wireless impedance sensor node (the WID3, $\underline{W}$ireless $\underline{I}$mpedance $\underline{D}$evice) for use in high-frequency impedance-based structural health monitoring (SHM), sensor diagnostics and validation, and low-frequency (< ~1 kHz) vibration data acquisition. The WID3 is equipped with an impedance chip that can resolve measurements up to 100 kHz, a frequency range ideal for many SHM applications. An integrated set of multiplexers allows the end user to monitor seven piezoelectric sensors from a single sensor node. The WID3 combines on-board processing using a microcontroller, data storage using flash memory, wireless communications capabilities, and a series of internal and external triggering options into a single package to realize a truly comprehensive, self-contained wireless active-sensor node for SHM applications. Furthermore, we recently extended the capability of this device by implementing low-frequency analog-to-digital and digital-to-analog converters so that the same device can measure structural vibration data. The compact sensor node collects relatively low-frequency acceleration measurements to estimate natural frequencies and operational deflection shapes, as well as relatively high-frequency impedance measurements to detect structural damage. Experimental results with application to SHM, sensor diagnostics and low-frequency vibration data acquisition are presented.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.5
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• pp.509-516
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• 2004

High-performance Si integrated passive process was developed using thick oxidation process and Cu-BCB process. This passive process leads to low-cost and high-quality RF module with a small form factor. The fabricated spiral inductor with 225 um inner diameter and 2.5 turns showed the inductance of 2.7 nH and the quality factor more than 30 in the frequency region of 1 ㎓ and above. Also WLCSP-type integrated passive devices were fabricated using the high-performance spiral inductors. The fabricated low pass filter had a parallel-resonance circuit inside the spiral inductor to suppress 2nd harmonics and showed about 0.5 ㏈ insertion loss at 2.45 ㎓. And also the high/low-pass balun had the insertion loss less than 0.5 ㏈ and the phase difference of 182 degrees at 2.45 ㎓.

• Proceedings of the KWS Conference
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• 2010.05a
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• pp.82-82
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• 2010

표면실장 공법을 통해 CSP 패키지를 보드에 실장 하는데 있어 무연솔더 접합부의 신뢰성에 영향을 미치는 인자 중 가장 중요한 것은 접합부에 형성되는 IMC (Intermetallic compound, 금속간화합물)인 것으로 알려져 있다. 접합부의 칩 부분에는 솔더와 칩의 UBM (Under bump metalization)이 접합하여 IMC가 형성되나, 보드 부분에는 솔더와 보드의 UBM 뿐만 아니라 그 사이에 솔더 페이스트가 함께 접합되어 IMC가 형성된다. 본 연구에서는 패키지의 신뢰성 연구를 위해 솔더 페이스트의 유무 및 두께에 따른 무연 솔더 접합부의 미세조직의 변화를 분석하였다. 본 실험에서는 Sn-3.0(Wt.%)Ag-0.5Cu 조성과 본 연구진에 의해 개발된 Sn-Ag-Cu-In 조성의 직경 $450{\mu}m$ 솔더 볼을 사용하였으며, 솔더 페이스트는 상용 Sn-3.0Ag-0.5Cu (ALPHA OM-325)를 사용하였다. 칩은 ENIG (Electroless nickel immersion gold) finish pad가 형성된 CSP (Chip scale package)를, 보드는 OSP (Organic solderability preservative)/Cu finish pad가 형성된 것을 사용하였다. 실험 방법은 보드를 솔더 페이스트 없이 플라즈마 처리 한 것, 솔더 페이스트를 $30{\mu}m$ 두께로 인쇄한 것, $120{\mu}m$의 두께로 인쇄한 것, 이렇게 3가지 조건으로 준비한 후, 솔더 볼이 bumping된 칩을 mounting하여, $242^{\circ}C$의 peak 온도 조건의 oven(1809UL, Heller)에서 reflow를 실시하여 패키지를 형성하였다. 이후 시편은 정밀 연마한 후, OM(Optical Microscopic)과 SEM(scanning electron microscope) 및 EDS(energy dispersive spectroscope)를 사용하여 솔더 접합부 IMC의 미세조직을 관찰, 분석하였다.

• Journal of Information Management
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• v.42 no.3
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• pp.1-26
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• 2011

The domain of LED is analyzed for describing the current status of Korea's R&D in the domain comparing with those of others quantitatively. Fourteen sub-domains of LED manufacturing technology are selected and the time span for analysis is ten-year: 2001-2010. Bibiliometric analysis is performed by the unit of publication, core researcher, institution and country. Strategical diagram is also produced with devised two indicators: NGI and NPI. As a result, Korea is competitive in the area of Chip Scale Package, but R&D supports in another promising areas, such as large-caliber sapphire wafer, are necessary. It is also revealed that research activities are expanded dominantly in academia, but practical technologies are developed in industrial circle. It is suggested that to support core corporate and to encourage industrial-academic collaboration is essential for systematical technology development and high achievement in prominent areas.