• Journal of Sensor Science and Technology
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• v.6 no.2
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• pp.115-122
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• 1997

In this paper, on-chp atomatic tuning circuit, using proposed integration level approximation technique, is designed to tuning of the variation of RC time-constant due to aging or temperature variation, etc. This circuit reduces the error, the difference between code values and real outputs of integrator, which is drawback of presented dual-slope tuning circuit and eliminates modulations of processing signals in integrated circuit due to fixed tuning codes during ordinary operation. This system is made up of simple integrator, A/D converter and digital control circuit and all capacitors are replaced by programed capacitor arrays in this system. This tuning circuit with 4 bit resolution achieves $-9.74{\sim}+9.68%$ of RC time constant error for 50% resistance variation.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.6
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• pp.324-332
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• 2005

In general, bus system consumes a very significant portion of power in a chip. Bus splitting can be used to reduce the energy dissipation and to reduce the Propagation delay on the bus by lowering the parasitic load of each bus segment. Data exchange probability distribution between a set of interconnected processing elements affects the average energy dissipation of the splitted bus architectures. In this research, we have developed tree-based bus splitting techniques and design methodologies, as an extension of horizontally aligned bus splitting. We have developed the methodology to select near-optimal bus architectures for low energy dissipation when data exchange probability distribution of a system is given. Experimental results show that the proposed techniques can reduce energy dissipation on the bus by up to 83$\%$.

• Journal of the Korea Society of Computer and Information
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• v.11 no.2 s.40
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• pp.159-167
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• 2006

Lipreading has been suggested as one of the methods to improve the performance of speech recognition in noisy environment. However, existing methods are developed and implemented only in software. This paper suggests a hardware design for real-time lipreading. For real-time processing and feasible implementation, we decompose the lipreading system into three parts; image acquisition module, feature vector extraction module, and recognition module. Image acquisition module capture input image by using CMOS image sensor. The feature vector extraction module extracts feature vector from the input image by using parallel block matching algorithm. The parallel block matching algorithm is coded and simulated for FPGA circuit. Recognition module uses HMM based recognition algorithm. The recognition algorithm is coded and simulated by using DSP chip. The simulation results show that a real-time lipreading system can be implemented in hardware.

• Journal of Astronomy and Space Sciences
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• v.19 no.4
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• pp.327-340
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• 2002

In this paper, we performed the design study of a wide-band digital autocorrelation spectrometer for the observation study of an extra-galaxy's spectral lines and the survey research of the special radio sources in field of the radio astronomy observational research. The autocorrelation spectrometer designed in this paper can be used to their spectrometer of any system because this spectrometer has a wide dynamic power and frequency range properties. In this system we use the aliasing sampling method to minimize the band loss. For the output signal of the correlator we can increase the signal processing speed using by a special DSP chip, the integration and the FFT using hardware, so this spectrometer can support the newest developed technique for the radio astronomy observation so called “On the fly” method.

• The KIPS Transactions:PartA
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• v.16A no.2
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• pp.79-88
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• 2009

In boundary scan architecture, test stimuli are shifted in one at a time and applied to the on-chip system logic. The test results are captured into the BSR and are examined by subsequent shifting. In this paper, we developed a continuous capture test architecture and test procedure using TPG based on boundary scan is used to performance test. In this architecture, test patterns of TPG are applied to CUT with system clock rate, and response of CUT is continuously captured by CBSR(Continuous Capture Boundary Scan Register) at the same rate and the captured results is shifted to TDO at the same rate. The suggested a continuous capture test architecture and test procedure is simulated by Altera Max+Plus 10.0. The simulation results shows the accurate operation and effectiveness of the proposed test architecture and procedure.

• Journal of Advanced Navigation Technology
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• v.17 no.3
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• pp.332-345
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• 2013

In this paper, recently, it is described to the piezoelectric transformer technology develops, because it was have to favorable characteristics such as electromagnetic-noise free, compact size, higher efficiency, and superior power density, flux linkage, noiseless, etc. its resonance frequency was used to output waveform of a sine wave. A rotor speed identification method of induction motor based on the theory of flux model reference adaptive system(FMRAS). The estimator execute the rotor speed identification so that the vector control of the induction motor may be achieved. The improved auxiliary variable of the model are introduced to perform accurate rotor speed estimation. The control system is composed of the PI controller for speed control and the current controller using space voltage vector PWM techniuqe and DC-DC converter. High speed calculation and processing for vector control is carried out by digital signal one chip microprocessor. Validity of the proposed control method is verified through simulation and experimental results.

• Journal of Korean Society of Forest Science
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• v.110 no.2
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• pp.217-232
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• 2021

This study calculated the productivity and cost of extraction and processing of logging residues by cut-to-length (CTL) and whole-tree (WT) harvesting methods. In addition, the comparative analysis of the characteristics of wood chip fuel to examine whether it was suitable for the fuel conditions of the energy facility. In the harvesting and processing system to produce the wood chips of logging residues the system productivity and cost of the CTL harvesting system were 1.6 Gwt/SMH and 89,865 won/Gwt, respectively. The productivity and cost of the WT harvesting system were 2.9 Gwt/SMH and 72,974 won/Gwt, respectively. The WT harvesting productivity increased 1.3times while harvesting cost decreased by 18.7% compared to the CTL harvesting system. The logging residues of wood chips were not suitable for CTL wood chips based on International Organization for Standardization (ISO 17225-4:2021) and South Korea standard (NIFoS, 2020), but the quality (A2, Second class) was improved through screening operation. The WT-unscreened wood chips conformed to NIFoS standard (second class) and did not conform to ISO but were improved through screening operation (Second class). In addition to the energy facility in plant A, all wood chips except CTL-unscreened wood chips were available through drying processing. The WT-unscreened wood chips were the lowest at 99,408 won/Gwt. Plants B, C, and D had higher moisture content than plant A, so WT-unscreened wood chips without drying processing were the lowest at 57,204 won/Gwt. Therefore, the production of logging residues should improve with operation methods that improve the quality of wood chips required for applying the variable biomass and energy facility.

• The Journal of the Korea Contents Association
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• v.6 no.9
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• pp.98-107
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• 2006

By improving performance of mobile machine(3D engine, 3D accelerator chip set, etc) and developing wireless network technology, a demand for actual contents of users is being increased rapidly. But, there are some difficulties yet for the speedy development of actual contents because of the limitation of development resources that is dependent on each mobile device's different performance. In general, much of the animated character-creation work for mobile environment is still done manually by experienced animator with the method of key frame processing. However, it needs a lot of time and more costs for creating motion. Additionally, it is possible to cause a distortion of motion. In this paper, I solved the difficulties by using a optical motion capture system, it was able to acquire accurate motion data more easily and quickly, and then it was possible to make 3D dance contents efficiently. Also, I showed techniques of key reduction and controlling frame number for using huge amounts of motion capture data in mobile environment which requires less resources. In making 3D dance contents, using an optical motion capture system was verified that it was more efficient to make and use actual-reality contents by creating actual character motion and by decreasing processing time than existing method.

• The KIPS Transactions:PartD
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• v.10D no.6
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• pp.1059-1066
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• 2003

In this paper, the magnetic sensing system is designed and implemented for the safe security in internet commerce system. When the payment is required inthe internet commerce system, the magnetic sensing system will get the information from a credit card without keyboard input and then encrypt and transmit the information to server. The credit card sensing system, which is proposed in this paper, is safe from keyboard hacking because it encrypts card information immediately in its internal chip and sends the information to host system. For the protection of information, the magnetic sensing system is basically based on a synchronous stream cipher cryptosystem which is related to a group of matrices. The size of matrices and the bits of keys for the best performances are determined for various cases. It is shown that for credit card payments. matrices of size 2 have good performance even at most 128bits keys with the consideration of inverse matrices. For authentication of general-purpose data, the magnetic sensing system needs more than 1.5KB data and in this case, the optimum size of matrices is 2 or 3 at more 256bits keys with consideration of inverse matrices.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.3
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• pp.699-707
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• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.