• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2003년도 추계학술발표논문집 (하)
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• pp.1375-1378
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• 2003

본 논문은 Rice 60K DNA Chip의 실험데이터를 기반으로 한 데이터베이스의 구축과 XML기반 검색시스템을 설계 및 구현에 대해 설명한다. 본 시스템은 실험 데이터를 저장하기 위하여 RDBMS 를 사용하고 Chip 데이터를 검색하기 위해 XML 기반의 검색시스템을 사용한다. 이를 위해 일반 속성으로 저장될 수 있는 데이터들은 데이터베이스의 테이블의 속성 값으로 저장하고, XML 기반 검색시스템을 통해 검색할 수 있도록 한다. 그리고 BLAST내용을 기반으로 하는 데이터는 테이블을 별도로 만들어서 검색이 가능하도록 한다.

• Journal of Welding and Joining
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• 제26권3호
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• pp.30-36
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• 2008

A flip-chip bonding system using IR laser with a wavelength of 1064 nm was developed and associated process parameters were analyzed using Taguchi methods. An infrared laser beam is designed to transmit through a silicon chip and used for transferring laser energy directly to micro-bumps. This process has several advantages: minimized heat affect zone, fast bonding and good reliability in the microchip bonding interface. Approximately 50 % of the irradiated energy can be directly used for bonding the solder bumps with a few seconds of bonding time. A flip-chip with 120 solder bumps was used for this experiment and the composition of the solder bump was Sn3.0Ag0.5Cu. The main processing parameters for IR laser flip-chip bonding were laser power, scanning speed, a spot size and UBM thickness. Taguchi methods were applied for optimizing these four main processing parameters. The optimized bump shape and its shear force were modeled and the experimental results were compared with them. The analysis results indicate that the bump shape and its shear force are dominantly influenced by laser power and scanning speed over a laser spot size. In addition, various effects of processing parameters for IR laser flip-chip bonding are presented and discussed.

• 전기학회논문지
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• 제58권10호
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• pp.2059-2063
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• 2009

This paper presents a programmable System-On-a-chip (SoC) for various embedded smart applications that need Neural Network computations. The system is fully implemented into a prototyping platform based on Field Programmable Gate Array (FPGA). The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using a real image processing application, an optical character recognition (OCR) system.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2009년도 추계학술발표대회
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• pp.41-42
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• 2009

현재 많은 임베디드 SoC(System-On-Chip)에는 캐시 메모리의 단점을 보완하기 위해 온-칩(On-Chip) SRAM, 즉, SPM(Scratchpad Memory)를 내장하고 있으며 SPM은 그 특성상 캐시 메모리와 달리 소프트웨어가 직접 관리해야 한다. 본 논문에서는 NUMA를 지원하는 Linux 상에서 이식성이 높으면서 단순하게 구현할 수 있는 SPM 관리 방법을 제안한다.

• 한국멀티미디어학회논문지
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• 제14권11호
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• pp.1401-1408
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• 2011

본 논문에서는 영상처리용 16개의 처리기를 위한 다중접근기억장치(Multi-Access Memory System) 및 병렬처리기의 칩을 설계하였다. 다중접근기억장치는 병렬접근 메모리 시스템의 한 종류로서 영상의 픽셀 데이터값에 8가지 타입으로 동시 접근이 가능하다. 또한 일정한 간격을 두고 픽셀 데이터값에 접근하는 것이 가능하다. 다중접근기억장치가 내장된 병렬처리기는 실제로 2003년에 구현되어진 적이 있다. 하지만 고해상도 영상을 실시간으로 처리하기에는 그 성능이 미치지 못하였다. 이에 본 논문에서는 이전의 시스템의 메모리 모듈(Memory Module)과 처리기(Processing Element)를 추가 확장하여 보다 개선된 병렬처리 시스템을 설계하였다. 이 시스템은 이전의 시스템보다는 3배, 시리얼 시스템보다는 6배 빠른 속도로 모폴로지컬 클로징(Morphological closing) 알고리즘의 수행이 가능하다.

• 대한의용생체공학회:의공학회지
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• 제21권5호
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• pp.513-517
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• 2000

본 논문에서 제안한 텔레메트리 시스템은 생체신호를 증거리로 전송하기 위한 RF 송신기와 전자파 간섭의 영향이 없는 광을 매체로하는 수신기로 구성된 시스템이다. 따라서 텔레메트리 시스템은 RF 송신부, 광 수신부 및 생체신호 처리를 위한 CMOS 원칩으로 구성되어있으며, 65$\times$125$\times$45mm의 크기이다. 제안된 텔레메트리 장점은 전자파에 노출을 최소화하면서 중거리(50m) 텔레메트리가 가능하여, 자유로운 상태에서의 모니터링이 가능하다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권2호
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• pp.117-126
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• 2012

This paper provides a method for compression transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively

• 전자공학회논문지C
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• 제34C권12호
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• pp.9-19
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• 1997

This paper describes the design and FPGA implementation of a system control unit within a multiprocessor chip which can be used as a node processor ina massively parallel processing (MPP) caches, memory management units, a bus unit and a system control unit. Major functions of the system control unit are locking/unlocking of the shared variables of protected access, synchronization of instruction execution among four integer untis, control of interrupts, generation control of processor's status, etc. The system control unit was modeled in very high level using verilog HDL. Then, it was simulated and verified in an environment where trap handler and external interrupt controller were added. Functional blocks of the system control unit were changed into RTL(register transfer level) model and synthesized using xilinx FPGA cell library in synopsys tool. The synthesized system control unit was implemented by Xilinx FPGA chip (XC4025EPG299) after timing verification.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1991년도 추계학술대회 논문집 학회본부
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• pp.219-222
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• 1991

It is difficult to adapt modern control theory to power conversion system for the price of real time control H/W and the difficulty of S/W implementation. But recent development of large integrated circuit make it possible that One-Chip microprocessor processes high speed arithmatic calculation used in control theory. Specially this chip is called Digital Signal Processing chip. So, this research developes high performance, high reliable digital control system using TMS320C30 of Texas Instrument for real time control in power conversion system.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2003년도 춘계학술대회 논문집
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• pp.1663-1667
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• 2003

This thesis is on tile development of LD(Laser Diode) chip tester and the control system based on graphical programming language(LabVIEW) to control the equipment. The LD chip tester is used to test the optic power and the optic spectrum of the LD Chip. The emitter size of LD chip and the diameter of the receiver(optic fiber) are very small. Therefore, in order to test each chip precisely, this tester needs high accuracy. However each motion part of the tester could not accomplish hish accuracy due to the limit of the mechanical performance. Hence. an image processing with machine vision was carried out in order to compensate for the error. and also a load test was carried out so as to reduce tile impact of load on chip while the probing motion device is working. The obtained results were within ${\pm}$5$\mu\textrm{m}$ error.