• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.203-211
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• 2013

UHF RFID tag designers usually ndde the chip impedance and read power sensitivity value obtained when a tag chip is mounted on a chip pad. The chip impedance, however, is not able to be supplied by chip manufacturer, since the chip impedance is varied according to tag designs and fabrication processes. Instead, the chip makers mostly supply the chip impedances measured on the bare dies. This study proposes a chip impedance and read power sensitivity evaluation method which requires a few simple auxiliary and some RF measuring equipment. As it is impractical to measure the chip impedance directly at mounted chip terminals, some form test fixture is employed and the effect of the fixture is modeled and de-embeded to determine the chip impedance and the read power sensitivity. Validity and accuracy of the proposed de-embed method are examined by using commercial RFID tag chips as well as a capacitor and a resistor the value of which are known.

• ETRI Journal
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• v.32 no.6
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• pp.969-971
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• 2010

Based on a de-embedding technique, a new method is proposed which is capable of evaluating chip impedance behavior over absorbed power in flip-chip bonded UHF radio frequency identification transponder ICs. For the de-embedding, four compact co-planar test fixtures, an equivalent circuit for the fixtures, and a parameter extraction procedure for the circuit are developed. The fixtures are designed such that the chip can absorb as much power as possible from a power source without radiating appreciable power. Experimental results show that the proposed modeling method is accurate and produces reliable chip impedance values related with absorbed power.

• Journal of Sensor Science and Technology
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• v.18 no.1
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• pp.42-47
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• 2009

In this paper we propose a microfluidic chip that measures the mechanical stiffness of cell membrane using impedance measurement. The microfluidic chip is composed of PDMS channel and a glass substrate with electrode. The proposed device uses patch-clamp technique to capture and deform a target cell and measures impedance of deformed cells. We demonstrated that the impedance increased after the membrane stretched and blocked the channel.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.12
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• pp.1148-1157
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• 2013

In a passive UHF RFID system, the impedance matching between tag antenna and chip as well as the protocol parameter settings in a reader plays important role in determination of the maximum read-range. Almost no paper, however, has dealt with the above issues in relation with the maximum read range. In this paper, two known methods (of using the value from data sheets and proprietary RFID tester) and our proposing method in chip impedance evaluation are compared in terms of maximum read range. The read range of tags whose antenna impedance is conjugate matched with the chip impedance obtained from the proposed method is improved maximum 73 % more than that of tags from the other methods.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.263-266
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• 2005

An UHF ($860{\sim}960MHz$) RFID tag antenna is optimized and designed using a genetic algorithm (GA). The tag antenna impedance should be matched to the conjugate of the impedance of the tag IC Chip. The chip impedance has real and capacitive imaginary parts due to the parasitic capacitance of the RFID chip. A GA linked with a commercially available antenna simulation program optimizes the UHF $860{\sim}960\;MHz$ tag antenna to match a commercially available RFID chip. This method shows that any RFID antenna can be designed for any commercial RFID chip with any impedance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.12
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• pp.1228-1235
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• 2014

Input impedance of UHF RFID tag chip is needed to design a tag. In determining the chip impedance, direct measurement method is adopted commonly. In this paper, problems generated from fixtures that interface between tag chip and coaxial-oriented measurement instrument are investigated and the result of the problems is shown, when the direct measurement method is applied. As an alternative to the method, a modeling method is proposed and its validity and accuracy are shown.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.12
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• pp.1671-1674
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• 2014

This paper presents a frequency-dependent cell impedance analysis chip for use in cancer and normal cell discrimination. The previous cell impedance analysis chips for flowing cells cannot allow enough time for cell-to-electrode contact to monitor frequency-dependent impedance response. Another type of the previous cell impedance analysis chips for the cells clamped by membranes need complex sample control for making stable cell-to-electrode contact. We present a new impedance analysis chip using the microchamber array, on which a PDMS cover is placed to make stable cell-to-electrode contact for the individual cell trapped in each microchamber; thus achieving frequency-dependent single-cell impedance analysis without complex sample control. Compared to the normal cells, the magnitude of NHBE cells is $60.07{\sim}97.41k{\Omega}$ higher than A549 cells in the frequency range of 95.6 kHz~2MHz and the phase of NHBE is $3.96^{\circ}{\sim}20.8^{\circ}$ higher than A549 cells in the frequency range of 4.37 kHz~2MHz, respectively. It is demonstrated experimentally that the impedance analysis chip performs frequency-dependent cell impedance analysis by making stable cell-to-electrode contact with simple sample control; thereby applicable to the normal cell and cancer cell discrimination.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1571-1574
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• 2002

This paper describes a circuit and its operations of a programmable digital on-chip terminator designed with CMOS circuits which are used in high speed I/O interface. The on-chip terminator matches external reference resistor with the accuracy of ${\pm}$ 4.1％ over process, voltage and temperature variation. The digital impedance codes are generated in programmable impedance controller (PIC), and the codes are sent to terminator transistor arrays at input pads serially to reduce the number of signal lines. The transistor array is thermometer-coded to reduce impedance glitches during code update and it is segmented to two different blocks of thermometer-coded transistor arrays to reduce the number of transistors. The terminator impedance is periodically updated during hold time to minimize inter-symbol interferences.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.131-137
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• 2016

In this paper, we analyze the impedance analysis of vertical interconnection through-silicon vias (TSV) that is being studied for the purpose of improving the degree of integration and an electric feature in 3D IC. Also, it is to improve the performance and the degree of integration of the three-dimensional integrated circuit system which can exceed the limits of conventional two-dimensional a IC. In the future, TSV technology in full-chip 3-dimensional integrated circuit system design is very important, and a study on the electrical characteristics of the TSV for high-density and high-bandwidth system design is very important. Therefore, we study analyze the impedance influence of the TSV in accordance with the distance and frequency in a multiple TSV-to-TSV for the purpose of designing a full-chip three-dimensional IC. The results of this study also are applicable to semiconductor process tools and designed for the manufacture of a full-chip 3D IC.

• Journal of electromagnetic engineering and science
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• v.11 no.3
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• pp.192-200
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• 2011

This paper proposes a new modeling method for estimating the impedance of an on-chip power/ground meshed plane. Frequency dependent R, L, and C parameters are extracted based on the proposed method so that the model can be applied from DC to high frequencies. The meshed plane model is composed of two parts: coplanar multi strip (CMS) and conductor-backed CMS. The conformal mapping technique and the scaled conductivity concept are used for accurate modeling of the CMS. The developed microstrip approach is applied to model the conductor-backed CMS. The proposed modeling method has been successfully verified by comparing the impedance of RLC circuit based on extracted parameters and the simulated impedance using a 3D-field solver.